Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 197 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) 8-Bit, 3-State Access Space
Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high.
Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
φ
CSn
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Write
High
T
3
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 8-Bit, 3-State Access Space