Datasheet

Section 5 Interrupt Controller
Page 140 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Yes
Program execution status
Interrupt generated?
NMI
Level 6 interrupt?
Mask level 5
or below?
Level 7 interrupt?
Mask level 6
or below?
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Hold
pending
Level 1 interrupt?
Mask level 0?
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2