Datasheet

Section 25 Electrical Characteristics
Page 1292 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(5) Timing of On-Chip Peripheral Modules
Table 25.35 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V, V
ref
= 4.5 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD
⎯ 40 ns Figure 25.74
Input data setup time t
PRS
25 ⎯ ns
Input data hold time t
PRH
25 ⎯ ns
PPG Pulse output delay time t
POD
⎯ 40 ns Figure 25.75
TPU Timer output delay time t
TOCD
⎯ 40 ns Figure 25.76
Timer input setup time t
TICS
25 ⎯ ns
Timer clock input setup time t
TCKS
25 ⎯ ns Figure 25.77
Timer clock
pulse width
Single-edge
specification
t
TCKWH
1.5 ⎯ t
cyc
Both-edge
specification
t
TCKWL
2.5 ⎯ t
cyc
8-bit timer Timer output delay time t
TMOD
⎯ 40 ns Figure 25.78
Timer reset input setup time t
TMRS
25 ⎯ ns Figure 25.80
Timer clock input setup time t
TMCS
25 ⎯ ns Figure 25.79
Timer clock
pulse width
Single-edge
specification
t
TMCWH
1.5 ⎯ t
cyc
Both-edge
specification
t
TMCWL
2.5 ⎯ t
cyc
WDT Overflow output delay time t
WOVD
⎯ 40 ns Figure 25.81
SCI Asynchronous t
Scyc
4 ⎯ t
cyc
Figure 25.82
Input clock
cycle
Synchronous 6 ⎯
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rising time t
SCKr
⎯ 1.5 t
cyc
Input clock falling time t
SCKf
⎯ 1.5
Transmit data delay time t
TXD
⎯ 40 ns Figure 25.83
Receive data setup time
(synchronous)
t
RXS
40 ⎯ ns
Receive data hold time
(synchronous)
t
RXH
40 ⎯ ns