Datasheet

Section 25 Electrical Characteristics
R01UH0310EJ0500 Rev. 5.00 Page 1259 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Tp
φ
A23 to A0
RAS5 to RAS2
UCAS
LCAS
OE, RD
HWR
D15 to D0
OE, RD
HWR
D15 to D0
AS
Tr T c1
t
CPW1
t
AC3
t
RCH
t
RCS1
Tc2 Tc1 Tc2
Read
Write
DACK and EDACK timing: when DDS = 0 and EDDS = 0
RAS timing: when RAST = 0
Note:
DACK0, DACK1
EDACK2, EDACK3
t
DACD1
t
DACD2
t
EDACD1
t
EDACD2
Figure 25.17 DRAM Access Timing: Two-State Burst Access