Datasheet

Section 25 Electrical Characteristics
R01UH0310EJ0500 Rev. 5.00 Page 1229 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Item Symbol Min. Max. Unit Test Conditions
Master 2.5 ⎯
SSU* SCS hold time
Slave
t
LAG
2.5 ⎯
t
cyc
Figures 25.48 to
25.51
Master ⎯ 40 Data output delay
time
Slave
t
OD
⎯ 40
ns
Master −5 ⎯ Data output hold
time
Slave
t
OH
0 ⎯
ns
Master 2.5 ⎯ Continuous
transmit delay time
Slave
t
TD
2.5 ⎯
t
cyc
Slave access time t
SA
⎯ 1 t
cyc
Slave out release time t
REL
⎯ 1 t
cyc
Figures 25.50
and 25.51
Note * SSU: Synchronous serial communication unit
25.1.4 A/D Conversion Characteristics
Table 25.11 A/D Conversion Characteristics
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz
Item Min. Typ. Max. Unit
Resolution 10 10 10 Bit
Conversion time 2.5* ⎯ ⎯ μs
Analog input capacitance ⎯ ⎯ 15 pF
Permissible signal source impedance ⎯ ⎯ 5 kΩ
Nonlinearity error ⎯ ⎯ ±3.5 LSB
Offset error ⎯ ⎯ ±3.5 LSB
Full-scale error ⎯ ⎯ ±3.5 LSB
Quantization error ⎯ ⎯ ±0.5 LSB
Absolute accuracy ⎯ ⎯ ±6.0 LSB
Note: * For 40 states at ADCLK = 16 MHz.