Datasheet

Section 25 Electrical Characteristics
R01UH0310EJ0500 Rev. 5.00 Page 1227 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(5) Timing of On-Chip Peripheral Modules
Table 25.10 Timing of On-Chip Peripheral Modules
Conditions: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
I/O ports Output data delay time t
PWD
⎯ 40 ns Figure 25.36
Input data setup time t
PRS
25 ⎯ ns
Input data hold time t
PRH
25 ⎯ ns
PPG Pulse output delay time t
POD
⎯ 40 ns Figure 25.37
TPU Timer output delay time t
TOCD
⎯ 40 ns Figure 25.38
Timer input setup time t
TICS
25 ⎯ ns
Timer clock input setup time t
TCKS
25 ⎯ ns Figure 25.39
Timer clock
pulse width
Single-edge
specification
t
TCKWH
1.5 ⎯ t
cyc
Both-edge
specification
t
TCKWL
2.5 ⎯ t
cyc
8-bit timer Timer output delay time t
TMOD
⎯ 40 ns Figure 25.40
Timer reset input setup time t
TMRS
25 ⎯ ns Figure 25.42
Timer clock input setup time t
TMCS
25 ⎯ ns Figure 25.41
Timer clock
pulse width
Single-edge
specification
t
TMCWH
1.5 ⎯ t
cyc
Both-edge
specification
t
TMCWL
2.5 ⎯ t
cyc
WDT Overflow output delay time t
WOVD
⎯ 40 ns Figure 25.43
SCI Asynchronous t
Scyc
4 ⎯ t
cyc
Figure 25.44
Input clock
cycle
Synchronous 6 ⎯
Input clock pulse width t
SCKW
0.4 0.6 t
Scyc
Input clock rising time t
SCKr
⎯ 1.5 t
cyc
Input clock falling time t
SCKf
⎯ 1.5
Transmit data delay time t
TXD
⎯ 40 ns Figure 25.45
Receive data setup time
(synchronous)
t
RXS
40 ⎯ ns
Receive data hold time
(synchronous)
t
RXH
40 ⎯ ns