Datasheet

Section 3 MCU Operating Modes
R01UH0310EJ0500 Rev. 5.00 Page 85 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Descriptions
4 ⎯ 0 R/W Reserved
The initial value should not be modified.
3 FLSHE 0 R/W Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMDBPR, and FLMSTR). If this
bit is set to 1, the flash memory control registers can
be read from and written to. If this bit is cleared to 0,
the flash memory control registers are not selected.
At this time, the contents of the flash memory control
registers are retained. 0 should be written to this bit in
LSIs other than the flash memory version.
0: Flash memory control registers are not selected for
addresses H'FFFEB0 to H'FFFEB3
1: Flash memory control registers are selected for
addresses H'FFFEB0 to H'FFFEB3
2 ⎯ 0 ⎯ Reserved
This bit is always read as 0 and cannot be modified.
1 EXPE ⎯ R/W External Bus Mode Enable
Sets the external bus mode. In modes 1, 2, and 4,
this bit is fixed at 1 and cannot be modified. In modes
3 and 7, this bit can be read from and written to.
Writing 0 to this bit when its value is 1 should only be
carried out when an external bus cycle is not being
executed.
0: External address space is disabled
1: External address space is enabled
0 RAME 1 R/W RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is canceled.
0: On-chip RAM is disabled
1: On-chip RAM is enabled