Datasheet

Section 21 Flash Memory
Page 1088 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
21.4.1 Read Array
This command reads the flash memory.
Write H'FFxx in the first bus cycle to shift the flash memory into the read array mode. Specify the
target read address in the next bus cycle after setting the CBIDB bit in FLMCR1 to 1, and data is
read from the address in 16-bit units.
As the flash memory stays in the read array mode until another command is issued, multiple
addresses can be read in sequence.
21.4.2 Read Status Register
This command reads the status register.
Write H'70xx in the first bus cycle, and the status register can be read in the second bus cycle
(refer to section 21.5, Status Register). Specify an even address in the program ROM, data flash,
or user boot ROM to read the status register.
Do not issue this command in the EW1 mode.
21.4.3 Clear Status Register
This command clears the status register.
Write H'50xx in the first bus cycle, and the FMERSF and FMPRSF bits in FLMSTR are cleared to
0.