Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1070 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(3) Data Reception
Figure 19.15 shows an example of reception operation, and figure 19.16 shows a flowchart
example of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit in SSER to 1, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a transfer
clock is input to the SSCK pin, the SSU receives data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit is set to 1, an RXI interrupt is generated. The RDRF
bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
LSI operation
User operation
SSI
SSCK
RDRF
Dummy-read SSRDR
RXI interrupt
generated
RXI interrupt
generated
RXI interrupt
generated
Read data from SSRDR Read data from SSRDR
Bit 0 Bit 7 Bit 0 Bit 0Bit 7 Bit 7
1 frame 1 frame
Figure 19.15 Example of Reception Operation
(Clock Synchronous Communication Mode)