Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1060 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(3) Data Reception
Figure 19.7 shows an example of reception operation, and figure 19.8 shows a flowchart example
of data reception. When receiving data, the SSU operates as shown below.
After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception.
In master mode, the SSU outputs a transfer clock and receives data. In slave mode, when a low
level signal is input to the SCS pin and a transfer clock is input to the SSCK pin, the SSU receives
data in synchronization with the transfer clock.
When 1-frame data has been received, the RDRF bit in SSSR is set to 1 and the receive data is
stored in SSRDR. At this time, if the RIE bit in SSER is set to 1, an RXI interrupt is generated.
The RDRF bit is automatically cleared to 0 by reading SSRDR.
When the RDRF bit has been set to 1 at the 8th rising edge of the transfer clock, the ORER bit in
SSSR is set to 1. This indicates that an overrun error (OEI) has occurred. At this time, data
reception is stopped. While the ORER bit in SSSR is set to 1, reception is not performed. To
resume the reception, clear the ORER bit to 0.
SCS
SSCK
Bit
0
Bit
0
Bit
1
Bit
1
Bit
2
Bit
2
Bit
3
Bit
3
Bit
4
Bit
4
Bit
5
Bit
5
Bit
6
Bit
6
Bit
7
Bit
7
SSI
RDRF
LSI operation
User operation
REI interrupt
generated
REI interrupt
generated
Dummy-read SSRDR0
Read SSRDR0
1 frame
SSRDR0
(LSB first transmission)
SSRDR0
(MSB first transmission)
1 frame
Figure 19.7 (1) Example of Reception Operation (SSU Mode)
When 8-Bit Data Length is Selected (SSRDR0 is Valid) with CPOS = 0 and CPHS = 0