Datasheet

Section 17 A/D Converter
Page 1014 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
17.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when the A/D conversion start delay time (t
D
) passes after the ADST bit in ADCSR is set to
1, then starts A/D conversion. Figure 17.6 shows the A/D conversion timing. Tables 17.5 and 17.6
show the A/D conversion time.
As shown in figure 17.6, the A/D conversion time (t
CONV
) includes the A/D conversion start delay
time (t
D
) and the input sampling time (t
SPL
). The length of t
D
varies depending on the timing of the
write access to ADCSR. The total conversion time therefore varies within the ranges indicated in
tables 17.5 and 17.6.
In scan mode, the values given in tables 17.5 and 17.6 apply to the first conversion time. The
values given in table 17.7 apply to the second and subsequent conversions. In either case, bit
EKCKS in ADCSR, and bits CKS1 and CKS0 in ADCR should be set so that the conversion time
is within the ranges indicated by the A/D conversion characteristics.
(1)
(2)
t
D
t
SPL
t
CONV
φ
Address
Write signal
Input sampling
timing
ADF
[Legend]
(1): ADCSR write cycle
(2): ADCSR address
t
D:
A/D conversion start delay time
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Figure 17.6 A/D Conversion Timing