Datasheet

Section 17 A/D Converter
Page 1012 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(2) One-Cycle Scan Mode
1. Set the ADSTCLR bit in ADCR to 1.
2. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
input, A/D conversion starts on the first channel in the specified channel group. Consecutive
A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a
maximum of eight channels (SCANE and SCANS = B'11) can be selected. When consecutive
A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and
CH2 of unit 0 = B'00, on AN4 when CH3 and CH2 of unit 1 = B'01, on AN8* when CH3 and
CH2 of unit 1 = B'10, or on AN12 when CH3 and CH2 of unit 1= B'11. When consecutive
A/D conversion is performed on eight channels, A/D conversion starts on AN0 when CH3 =
B'0 or on AN8* when CH3 = B'1.
3. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
transferred to the corresponding ADDR of each channel.
4. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated.
5. The ADST bit is automatically cleared when A/D conversion is completed for all of the
channels that have been selected. A/D conversion stops and the A/D converter enters a wait
state.
Note: * Only possible in the H8S/2426 group and H8S/2426R group.