Datasheet

Section 16 I2C Bus Interface 2 (IIC2)
R01UH0310EJ0500 Rev. 5.00 Page 987 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
16.6 Bit Synchronous Circuit
In master mode,
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up
resistance)
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 16.18
shows the timing of the bit synchronous circuit and table 16.4 shows the time when SCL output
changes from low to Hi-Z then SCL is monitored.
SCL
VIH
SCL monitor
timing reference
clock
Internal SCL
Figure 16.18 Timing of the Bit Synchronous Circuit
Table 16.4 Time for monitoring SCL
CKS3 CKS2 CSK1 CSK0 Time for monitoring SCL
0 * * 7.5 tcyc
0 41.5 tcyc 0
1
0
1
1 *
19.5 tcyc
0 * * 17.5 tcyc
0 0
1
85.5 tcyc
1
1
1 * 41.5 tcyc