Datasheet

Section 16 I2C Bus Interface 2 (IIC2)
R01UH0310EJ0500 Rev. 5.00 Page 975 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
TDRE
TEND
ICDRS
ICDRR
[1] Clear TDRE after clearing
TEND and TRS
[2] Read ICDRR (dummy read)
[3] Read ICDRR
1
A
2134567899
A
TRS
RDRF
SCL
(master output)
SDA
(master output)
SDA
(slave output)
Bit 7
Master transmit mode Master receive mode
Bit 7Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
User
processing
Data 1
Data 1
Figure 16.7 Master Receive Mode Operation Timing 1