Datasheet

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User's Manual

All information contained in these materials, including products and product

specifications, represents information on the product at the time of publication and is

subject to change by Renesas Electronics Corp. without notice. Please review the

latest information published by Renesas Electronics Corp. through various means,

including the Renesas Electronics Corp. website (http://www.renesas.com).

H8S/2426, H8S/2426R, H8S/2424 Group

User’s Manual: Hardware

Rev.5.00 Sep 2012

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/2400 Series

H8S/2426 R4F2426

R4S2426

H8S/2426R R4F2426R

R4S2426R

H8S/2424 R4F2424

R4S2424

www.renesas.com

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Summary of content (1418 pages)

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User's Manual 16 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
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Page ii of xxx
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.
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2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name".
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3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. (1) [Table of Bits] Bit (2) (3) (4) (5) Bit Name − − Initial Value R/W Description 0 0 R R Reserved These bits are always read as 0. 13 to 11 ASID2 to ASID0 All 0 R/W Address Identifier These bits enable or disable the pin function.
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4. Description of Abbreviations The abbreviations used in this manual are listed below.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Specifications.................................................................
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2.8 2.9 2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)................. 75 2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn..... 75 2.7.5 Absolute Address—@aa:8/@aa:16/@aa:24/@aa:32.............................................. 75 2.7.6 Immediate—#xx:8/#xx:16/#xx:32.......................................................................... 76 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 76 2.7.
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Section 5 Interrupt Controller ............................................................................107 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Features.............................................................................................................................. 107 Input/Output Pins............................................................................................................... 109 Register Descriptions ...........................................................................
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6.3.6 6.4 6.5 6.6 6.7 Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 167 6.3.7 Bus Control Register (BCR) ................................................................................. 168 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 170 6.3.9 DRAM Control Register (DRAMCR) .................................................................. 171 6.3.
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6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.7.10 Byte Access Control ............................................................................................. 234 6.7.11 Burst Operation..................................................................................................... 236 6.7.12 Refresh Control..................................................................................................... 241 6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface.....
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6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 312 6.15.4 BREQO Output Timing ........................................................................................ 313 6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 313 Section 7 DMA Controller (DMAC).................................................................315 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Features....................................................
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Section 8 EXDMA Controller (EXDMAC) ......................................................407 8.1 8.2 8.3 8.4 8.5 8.6 Features.............................................................................................................................. 407 Input/Output Pins............................................................................................................... 409 Register Descriptions .................................................................................................
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9.4 9.5 9.6 9.7 9.8 Location of Register Information and DTC Vector Table ................................................. 485 Operation ........................................................................................................................... 489 9.5.1 Normal Mode........................................................................................................ 492 9.5.2 Repeat Mode...................................................................................................
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10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.3.3 Port 3 Register (PORT3)....................................................................................... 570 10.3.4 Port 3 Open Drain Control Register (P3ODR) ..................................................... 571 10.3.5 Pin Functions ........................................................................................................ 572 Port 4.......................................................................................................
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10.11 10.12 10.13 10.14 10.15 10.16 10.10.5 Port B Open Drain Control Register (PBODR) .................................................... 625 10.10.6 Pin Functions ........................................................................................................ 626 10.10.7 Port B Input Pull-Up MOS States......................................................................... 634 Port C ...........................................................................................................
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10.16.1 Port H Data Direction Register (PHDDR)............................................................ 682 10.16.2 Port H Data Register (PHDR)............................................................................... 684 10.16.3 Port H Register (PORTH)..................................................................................... 684 10.16.4 Port H Open Drain Control Register (PHODR).................................................... 685 10.16.5 Pin Functions ................................
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11.5 11.6 11.7 11.8 11.9 11.10 11.4.6 Phase Counting Mode........................................................................................... 771 Interrupt Sources................................................................................................................ 779 DTC Activation.................................................................................................................. 783 DMAC Activation...........................................................................
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12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) .................. 822 12.4.7 Inverted Pulse Output ........................................................................................... 824 12.4.8 Pulse Output Triggered by Input Capture ............................................................. 825 12.5 Usage Notes .......................................................................................................................
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13.8.6 Mode Setting with Cascaded Connection ............................................................. 851 13.8.7 Module Stop Function Setting .............................................................................. 851 13.8.8 Interrupts in Module Stop State ............................................................................ 851 Section 14 Watchdog Timer (WDT) ................................................................. 853 14.1 Features..............................................
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15.5 15.6 15.7 15.8 15.9 15.10 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode..................................................................................................................... 902 15.4.3 Clock..................................................................................................................... 903 15.4.4 SCI Initialization (Asynchronous Mode).............................................................. 904 15.4.
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Section 16 I2C Bus Interface 2 (IIC2)................................................................955 16.1 Features.............................................................................................................................. 955 16.2 Input/Output Pins............................................................................................................... 957 16.3 Register Descriptions ..................................................................................................
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17.5 Interrupt Source ............................................................................................................... 1017 17.6 A/D Conversion Accuracy Definitions ............................................................................ 1018 17.7 Usage Notes ..................................................................................................................... 1020 17.7.1 Module Stop Function Setting ..........................................................................
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19.4.1 Transfer Clock .................................................................................................... 1051 19.4.2 Relationship of Clock Phase, Polarity, and Data ................................................ 1051 19.4.3 Relationship between Data Input/Output Pins and Shift Register ...................... 1052 19.4.4 Communication Modes and Pin Functions ......................................................... 1053 19.4.5 SSU Mode......................................................
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21.8 21.9 21.10 21.11 Boot Mode ....................................................................................................................... 1099 SCI Boot Mode ................................................................................................................ 1099 Serial Communication Interface Specification for Boot Mode........................................ 1100 Programmer Mode ......................................................................................................
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23.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR...................................... 1161 23.5.6 Notes on Clock Division Mode........................................................................... 1162 Section 24 List of Registers............................................................................. 1163 24.1 Register Addresses (Address Order)................................................................................ 1164 24.2 Register Bits.................................................
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25.5.3 AC Characteristics .............................................................................................. 1302 25.5.4 A/D Conversion Characteristics ......................................................................... 1309 25.5.5 D/A Conversion Characteristics ......................................................................... 1310 25.5.6 Flash Memory Characteristics ............................................................................ 1310 25.6 Timing Charts (5-V Version)..
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Section 1 Overview 1.1 Features The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group are CISC (Complex Instruction Set Computer) microprocessors that integrate an H8S/2600 CPU core, which has an internal 16-bit architecture and is upward-compatible with Renesas-original H8/300, H8/300H, and H8S CPUs.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview 1.1.2 Overview of Specifications The specifications of this LSI are summarized in table 1.1. Table 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Type CPU Interrupts (sources) Module/ Function MCU operating mode Interrupt controller Section 1 Overview Description • Mode 1: Expanded mode with on-chip ROM disabled, 16-bit bus (MD2 and MD1 pins are low and MD0 pin is high) • Mode 2: Expanded mode with on-chip ROM disabled, 8-bit bus (MD2 pin is low, MD1 pin is high, and MD0 pin is low) • Mode 3: Boot mode (MD2 pin is low and MD1 and MD0 pins are high) • Mode 4: Expanded mode with on-chip ROM enabled,
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Type DMA Module/ Function EXDMA controller (EXDMAC) Description • DMA transfer is possible on two channels • Two activation sources (auto-request and external request) • Two transfer modes (normal mode and block transfer mode) • Dual address mode or single address mode can be selected • 16-Mbyte address space can be specified directly • Repeat area can be set Note: * EXDMAC is supported only by the H8S/2426 Group and H8S/2426R Group.
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H8S/2426, H8S/2426R, H8S/2424 Group Type Clock Module/ Function Section 1 Overview Description Clock pulse • generator • (CPG) This LSI has a single on-chip clock pulse generator circuit Consists of an oscillator, a system-clock PLL circuit, a divider, and the system clock frequency can be changed System clock (φ) cycle: 8 to 33 MHz • Six power-down modes Divided clock mode, sleep mode, module stop function, all module clock stop mode, software standby mode, and hardware standby mode A/D converter
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Type Timer Module/ Function 16-bit timer pulse unit (TPU) 8-bit timer (TMR) Description • 16-bit timer × 12 channels (general pulse timer unit) • Eight counter input clocks can be selected for each channel • Maximum 16-pulse input/output (when external expanded mode is set) • Maximum 32-pulse input/output (when single-chip mode is set) • Counter clear operation, simultaneous write to multiple timer counters (TCNT), simultaneous clearing by
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H8S/2426, H8S/2426R, H8S/2424 Group Type Highfunction communications Module/ Function 2 I C bus interface 2 (IIC2) Synchronou s serial communicati on unit (SSU) I/O ports Section 1 Overview Description • Four channels • Continuous transmission/reception • Start and stop conditions generated automatically in master mode • Selection of acknowledge output levels when receiving • Automatic loading of acknowledge bit when transmitting • Bit synchronization/wait function • One channel • Mast
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Type Module/ Function Operating frequency/ power supply voltage Description • Operating frequency: 8 to 33 MHz • Power supply voltage 3-V version: VCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V 5-V version: VCC = 4.5 to 5.5 V, AVCC = 4.5 to 5.5 V • Supply current 3-V version: 45 mA typ (VCC = 3.3 V, AVCC = 3.3 V, φ = 33 MHz) 5-V version: 45 mA typ (VCC = 5.0 V, AVCC = 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 1.2 Section 1 Overview List of Products Table 1.2 lists the products and figure 1.1 shows how to read the product type name. Table 1.2 Product Code Lineup Guaranteed Flash Operating Temperature Memory Size RAM Size Voltage Range Package Code −20°C +75°C PLQP0144KA-A Product Type Type Code H8S/2426R R4F24269NVRFQV 256 Kbytes 64 Kbytes 3.0 to 3.6V R4F24268NVRFQV 256 Kbytes 48 Kbytes 3.0 to 3.6V R4F24265NVRFQV 128 Kbytes 48 Kbytes 3.0 to 3.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Guaranteed Flash Operating Temperature Memory Size RAM Size Voltage Range Package Code H8S/2426 Group R4F24269NVFQV 256 Kbytes 64 Kbytes 3.0 to 3.6V −20°C +75°C PLQP0144KA-A R4F24268NVFQV 256 Kbytes 48 Kbytes 3.0 to 3.6V Product Type Page 10 of 1384 Type Code R4F24265NVFQV 128 Kbytes 48 Kbytes 3.0 to 3.6V R4S24262NVFQV ⎯ 64 Kbytes 3.0 to 3.6V R4S24261NVFQV ⎯ 48 Kbytes 3.0 to 3.6V R4F24269NFQV 256 Kbytes 64 Kbytes 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Guaranteed Flash Operating Temperature Memory Size RAM Size Voltage Range Package Code H8S/2426 Group R4F24269DVLPV 256 Kbytes 64 Kbytes 3.0 to 3.6V −40°C +85°C PTLG0145JB-A R4F24268DVLPV 256 Kbytes 48 Kbytes 3.0 to 3.6V −20°C +75°C PLQP0120KA-A Product Type Type Code R4F24265DVLPV 128 Kbytes 48 Kbytes 3.0 to 3.6V R4S24262DVLPV ⎯ 64 Kbytes 3.0 to 3.6V R4S24261DVLPV ⎯ 48 Kbytes 3.0 to 3.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Guaranteed Flash Operating Temperature Memory Size RAM Size Voltage Range Package Code H8S/2424 Group R4F24249NVFPV 256 Kbytes 64 Kbytes 3.0 to 3.6V −20°C +75°C PLQP0120LA-A R4F24248NVFPV 256 Kbytes 48 Kbytes 3.0 to 3.6V Product Type Page 12 of 1384 Type Code R4F24245NVFPV 128 Kbytes 48 Kbytes 3.0 to 3.6V R4S24242NVFPV ⎯ 64 Kbytes 3.0 to 3.6V R4S24241NVFPV ⎯ 48 Kbytes 3.0 to 3.6V R4F24249NFPV 256 Kbytes 64 Kbytes 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Product type name R 4 F 2426 9 N V R FQ V Indicates treatment of outer leads V: Sn-2Bi U: Sn Indicates the package FQ: PLQP0144KA-A LP: PTLG0145JB-A FP: PLQP0120LA-A FA: PLQP0120KA-A Indicates the product group R: H8S/2426R group None: H8S/2426 group or H8S/2424 group Indicates the operating voltage V: 3.0 to 3.6 V None: 4.5 to 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Bus controller Port A PB7/A15/TIOCB8/TCLKH PB6/A14/TIOCA8 PB5/A13/TIOCB7/TCLKG PB4/A12/TIOCA7 PB3/A11/TIOCD6/TCLKF PB2/A10/TIOCC6/TCLKE PB1/A9/TIOCB6 PB0/A8/TIOCA6 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 P35/OE-B*2/CKE-B*1/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD EXDMAC WDT RAM SCI × 5 channels IIC2 × 4 channels TPU × 12 cha
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H8S/2426, H8S/2426R, H8S/2424 Group Port A Port G P85/PO5-B/TIOCB4-B/TMO1-B/SCK3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 PC7/A7/TIOCB11 PC6/A6/TIOCA11 PC5/A5/TIOCB10 PC4/A4/TIOCA10 PC3/A3/TIOCD9 PC2/A2/TIOCC9 PC1/A1/TIOCB9 PC0/A0/TIOCA9 P35/OE-B*/SCK1/SCL0 P34/SCK0/SCK4-A/SDA0 P33/RxD1/SCL1 P32/RxD0/IrRxD/SDA1 P31/TxD1 P30/TxD0/IrTxD WDT SCI × 5 channels RAM IIC2 × 4 channels 8-bit D/A converter (2 channels) TPU × 12 channels (two units) 10-bit A/D converter (total of 10 cha
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin Description 1.4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview 1 2 3 4 5 6 7 8 9 10 11 12 13 A Vss MD1 MD0 P32 P35 P50 AVss P94 P90 P44 P40 PG2 PG3 B MD2 Vcc P31 P34 P51 PG4 P93 P47 P45 P42 AVcc Vref PG1 C PC0 P80 PC1 P30 P33 P52 PG5 P92 P46 P43 P41 PG0 P65 D PC4 PC2 PC3 P53 PG6 P97 P96 P95 P91 P63 PJ0 P64 STBY E PC7 Vss PC5 PB0 NC Vss Vcc PJ1 Vcc F PB3 PC6 PB1 Vss PF7 Vss XTAL EXTAL G PB6 PB2 PA0 PB4 PF6 RES PF5 PLLVss
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H8S/2426, H8S/2426R, H8S/2424 Group 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PG1/CS1 PG0/CS0 STBY VSS P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 VCC VCC EXTAL XTAL VSS PF7/φ PLLVSS RES PLLVCC PF6/AS/AH PF5/RD PF4/HWR PF3/LWR/SSO0-C PF2/CS6/LCAS*3/SSI0-C PF1/CS5/UCAS*3/SSCK0-C PF0/WAIT-A/OE-A*3/ADTRG0-B/SCS0-C PD7/D15/AD15 PD6/D14/AD14 PD5/D13/AD13 PD4/D12/AD12 PD3/D11/AD11 PD2/D10/AD10 PD1/D9/AD9 PD0/D8/AD8 Section 1 Overview 91 92 93
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H8S/2426, H8S/2426R, H8S/2424 Group 1.4.2 Table 1.3 Section 1 Overview Pin Assignments in Each Operating Mode Pin Assignments in Each Operating Mode of H8S/2426 Group and H8S/2426R Group Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 1.4 Section 1 Overview Pin Assignments in Each Operating Mode of H8S/2424 Group Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No.
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H8S/2426, H8S/2426R, H8S/2424 Group 1.4.3 Section 1 Overview Pin Functions Table 1.5 Pin Functions Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Power supply VCC 4, 72, 98, 99 B2, N12, E11, E13 2, 60, 83, 84 Input For connection to the power supply. VCC pins should be connected to the system power supply.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Operating mode control MD2 1 B1 1 Input MD1 144 A2 120 These pins set the operating mode. These pins should not be changed during operation. MD0 143 A3 119 RES 92 G11 77 Input Reset pin. When this pin is driven low, the chip is reset.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Bus control CS7 to CS0 38 to 35, 110 to 107 M2, N2, M1, L1, A13, A12, B13, C12 29, 71, 70, 106, 92 to 89 Output Signals that select division areas 7 to 0 in the external address space AS 90 G10 75 Output When this pin is low, it indicates that address output on the address bus is valid.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Bus control Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function DQMU* 85 H12 ⎯ Output Upper data mask enable signal for accessing the 16-bit continuous synchronous DRAM space. Also functions as the data mask enable signal for accessing the 8-bit continuous synchronous DRAM space.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Interrupt signals NMI 40 N1 32 Input Nonmaskable interrupt request pin. This pin should be fixed high when not used. IRQ15-A to IRQ8-A*2 86, 85, 106 to 104, 83 to 81 H10, H12, C13, D12, D10, J10, K13, J12 ⎯ Input These pins request a maskable interrupt.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function 16-bit timer TCLKH pulse TCLKG unit (TPU) TCLKF 22 H2 20 Input 20 H4 18 External clock input pins of the timer.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function 16-bit timer TIOCA6 pulse TIOCB6 unit (TPU) TIOCC6 14 E4 12 15 F3 13 Input/ output TGRA_6 to TGRD_6 input capture input/output compare output/PWM output pins. 16 G2 14 TIOCD6 17 F1 15 TIOCA7 19 G4 16 TIOCB7 20 H4 18 Input/ output TGRA_7 and TGRB_7 input capture input/output compare output/PWM output pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function 8-bit timer (TMR) TMO0-A 105 D12 46 Output TMO1-A 106 C13 47 Waveform output pins with output compare function. TMO0-B 135 C6 111 TMO1-B 61 M8 50 TMCI0-A 83 J10 44 Input External event input pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function Serial communication interface (SCI)/ Smart Card interface (SCI_0 with IrDA function) SCK4-A 138 B4 114 27 H3 25 Input/ output Clock input/output pins. SCK4-B SCK3 61 M8 50 SCK2 135 C6 111 SCK1 137 A5 113 SCK0 138 B4 114 I2C bus interface 2 (IIC2) SCL3 134 B5 110 I2C clock input/output pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type A/D converter Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function ⎯ Input Analog input pins. D8 104 Input Analog input pins. A8 103 124 to 121 B7, C8, D9, A9 ⎯ Input Analog input pins. AN7_0 to AN0_0 120 to 113 B8, C9, B9, A10, 102 to 95 C10, B10, C11, A11 Input Analog input pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function I/O ports P47 to P40 120 to 113 B8, C9, B9, A10, 102 to 95 C10, B10, C11, A11 Input 8-bit input pins. P53 to P50 136 to 133 D4, C6, B5, A6 112 to 109 Input/ output 4-bit input/output pins. P65 to P60*2 106 to 104, 83 to 81 C13, D12, D10, J10, K13, J12 ⎯ Input/ output 6-bit input/output pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 1 Overview Pin No. H8S/2426, H8S/2426R H8S/2424 PLQP0120LA-A, Type Symbol PLQP0144KA-A PTLG0145JB-A PLQP0120KA-A I/O Function I/O ports PF7 to PF0 94, 90 to 84 F10, G10, G12, H11, J13, H10, H12, J11 Input/ output 8-bit input/output pins. PG6 to PG0 132 to 130, 110 to 107 D5, C7, B6, A13, 108 to 106, A12, B13, C12 92 to 89 Input/ output 7-bit input/output pins. PH3 to PH0*2 38 to 35 M2, N2, M1, L1 ⎯ Input/ output 4-bit input/output pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Section 2 CPU The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending on the product.
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Section 2 CPU H8S/2426, H8S/2426R, H8S/2424 Group 16 ÷ 8-bit register-register divide: 12 states 16 × 16-bit register-register multiply: 3 states 32 ÷ 16-bit register-register divide: 20 states • Two CPU operating modes Normal mode* Advanced mode Note: * Normal mode is not available in this LSI. • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Execution States Instruction Mnemonic H8S/2600 H8S/2000 MULXU MULXU.B Rs, Rd 2* 12 MULXU.W Rs, ERd 2* 20 MULXS.B Rs, Rd 3* 13 MULXS.W Rs, ERd 3* 21 CLRMAC CLRMAC 1* Not supported LDMAC LDMAC ERs, MACH 1* LDMAC ERs, MACL 1* STMAC STMAC MACH, ERd 1* STMAC MACL, ERd 1* MULXS Note: 2.1.2 * The number of execution states is incremented following a MAC instruction.
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Section 2 CPU H8S/2426, H8S/2426R, H8S/2424 Group • Higher speed Basic instructions execute twice as fast. Note: Normal mode is not available in this LSI. 2.1.3 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements. • Additional control register One 8-bit and two 32-bit control registers have been added. • Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.2 Section 2 CPU CPU Operating Modes The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space. The mode is selected by the mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. • Address Space The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) EXR*1 SP Reserved*1 *3 (SP*2 ) CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used, it is not stored on the stack.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.2.2 Section 2 CPU Advanced Mode • Address Space Linear access is provided to a 16-Mbyte maximum address space. • Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. • Instruction Set All instructions and addressing modes can be used.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.3 Section 2 CPU Address Space Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU 2.4 Registers The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiplyaccumulate register (MAC).
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H8S/2426, H8S/2426R, H8S/2424 Group 2.4.1 Section 2 CPU General Registers The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) 2.4.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.4.4 Section 2 CPU Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Bit Bit Name Initial Value R/W Description 2 Z Undefined R/W Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. 1 V Undefined R/W Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise. 0 C Undefined R/W Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.5 Section 2 CPU Data Formats The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats in general registers.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.9 General Register Data Formats (2) Page 60 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.5.2 Section 2 CPU Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU 2.6 Instruction Set The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in table 2.1. Table 2.
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H8S/2426, H8S/2426R, H8S/2424 Group 3. 4. 2.6.1 Section 2 CPU Cannot be used in this LSI. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Symbol Description → Move ∼ NOT (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). Table 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.4 Section 2 CPU Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Table 2.4 Arithmetic Operations Instructions (2) Instruction Size*1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.5 Section 2 CPU Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.7 Section 2 CPU Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ [~ ( of )] → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc ⎯ Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 2.9 Section 2 CPU System Control Instructions Instruction Size* Function TRAPA ⎯ Starts trap-instruction exception handling. RTE ⎯ Returns from an exception-handling routine. SLEEP ⎯ Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the contents of a general register or memory, or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B ⎯ if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W ⎯ if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.11 Instruction Formats (Examples) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address modes are different in each instruction. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.7.3 Section 2 CPU Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction code, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Table 2.12 Absolute Address Access Ranges Absolute Address Data address Normal Mode* 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) Program instruction address Note: 2.7.6 * Advanced Mode H'000000 to H'FFFFFF 24 bits (@aa:24) Not available in this LSI.
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H8S/2426, H8S/2426R, H8S/2424 Group 2.7.8 Section 2 CPU Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Note: Normal mode is not available in this LSI. Table 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
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Section 2 CPU 2.8 H8S/2426, H8S/2426R, H8S/2424 Group Processing States The H8S/2600 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state transitions. • Reset State The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 2 CPU End of bus request Bus request pt ion ha ex nd ce lin pt g io n ha nd lin g ce En d or ex st f of ue d En Re q Exception handling state n Bus-released state Sleep mode t ues q t re rrup Inte =0 BY SS EEP tion SL truc ins io = 1 ruct BY nst SS EP i E SL of bu s re Bu qu sr es eq t ue st Program execution state External interrupt request Software standby mode RES = High Reset state*1 STBY = High, RES = Low Reset state Hardware st
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Section 2 CPU 2.9 Usage Note 2.9.1 Usage Notes on Bit-wise Operation Instructions H8S/2426, H8S/2426R, H8S/2424 Group The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore, special care is necessary to use these instructions for the registers and the ports that include writeonly bit.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Operating Mode Selection The H8S/2426 Group, H8S/2426R Group, and H8S/2424 Group have five operating modes (modes 1 to 4 and 7). The operating mode is selected by the setting of mode pins (MD2 to MD0). Modes 1, 2, and 4 are externally expanded modes in which the CPU can access an external memory and peripheral devices.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes 3.2 Register Descriptions The following registers are related to operating mode setting. • • Mode control register (MDCR) System control register (SYSCR) 3.2.1 Mode Control Register (MDCR) MDCR monitors the current operating mode of this LSI. Bit Bit Name Initial Value R/W Descriptions 7 to 3 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes Bit Bit Name Initial Value R/W Descriptions 4 ⎯ 0 R/W Reserved 3 FLSHE 0 R/W Flash Memory Control Register Enable The initial value should not be modified. Controls CPU access to the flash memory control registers (FLMCR1, FLMDBPR, and FLMSTR). If this bit is set to 1, the flash memory control registers can be read from and written to. If this bit is cleared to 0, the flash memory control registers are not selected.
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Section 3 MCU Operating Modes 3.3 Operating Mode Descriptions 3.3.1 Mode 1 H8S/2426, H8S/2426R, H8S/2424 Group The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F to H function as bus control signals. The initial bus mode immediately after a reset is 16 bits, with 16-bit access to all areas.
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H8S/2426, H8S/2426R, H8S/2424 Group 3.3.4 Section 3 MCU Operating Modes Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. The program in the on-chip ROM connected to the first half of area 0 is executed. Ports A to C function as input ports immediately after a reset, but can be set to function as an address bus depending on each port register setting. Port D functions as a data bus and parts of ports F to H function as bus control signals.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes 3.3.6 Pin Functions Table 3.2 shows the pin functions in each operating mode. Table 3.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes RAM: 64 Kbytes/48 Kbytes ROM: 256 Kbytes RAM: 64 Kbytes/48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) Mode 3 (Boot mode) H'000000 H'000000 On-chip ROM H'040000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 H'FE8000 Reserved area*4 Reserved
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes ROM: 256 Kbytes RAM: 64 Kbytes / 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) ROM: 256 Kbytes RAM: 64 Kbytes / 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'040000 H'040000 Reserved area*4 Reserved area*4 H'080000 H'080000 External address space/ Reserved area*2*4 External address space H'F00000 H'F00000 Data flash area 8 Kbytes Data fla
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes RAM: 48 Kbytes ROM: 128 Kbytes RAM: 48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 Mode 3 (Boot mode) H'000000 On-chip ROM H'020000 Reserved area*4 H'080000 External address space External address space/ Reserved area*2*4 H'F00000 Data flash area 8 Kbytes H'F02000 External address space/ Reserved area*2*4 H'FE8000 H'FE8000 Reserved area*4 Reserved area*4 H'FF0000 H'FF0000 On-chip RAM/ External address
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes ROM: 128 Kbytes RAM: 48 Kbytes Mode 7 (Single-chip activation expanded mode with on-chip ROM enabled) ROM: 128 Kbytes RAM: 48 Kbytes Mode 4 (Expanded mode with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'020000 On-chip ROM H'020000 Reserved area*4 Reserved area*4 H'080000 H'080000 External address space/ Reserved area*2*4 External address space H'F00000 H'F00000 Data flash area 8 Kbytes Data flash area 8 Kbytes H'F020
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H8S/2426, H8S/2426R, H8S/2424 Group Section 3 MCU Operating Modes RAM: 64 Kbytes /48 Kbytes Modes 1 and 2 (Expanded mode with on-chip ROM disabled) H'000000 External address space H'FE8000 H'FEC000 H'FF0000 H'FFC000 H'FFD000 Reserved area*2 On-chip RAM/External address space/ Reserved area*1*3 On-chip RAM/External address space*1*3 Reserved area*2 External address space H'FFFA00 Internal I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF Internal I/O registers Notes: 1.
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Section 3 MCU Operating Modes Page 94 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling 4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Since the usable modes differ depending on the product, for details on each product, refer to section 3, MCU Operating Modes. Table 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling Vector Address*1 Exception Source External interrupt IRQ7 5 IRQ8* 5 IRQ9* External interrupt Vector Number Normal Mode*2 Advanced Mode 23 H'002E to H'002F H'005C to H'005F 24 H'0030 to H'0031 H'0060 to H'0063 25 H'0032 to H'0033 H'0064 to H'0067 IRQ10* 5 26 H'0034 to H'0035 H'0068 to H'006B IRQ11* 5 27 H'0036 to H'0037 H'006C to H'006F IRQ12* 5 28 H'0038 to H'0039 H'0070 to H'0073 IRQ13* 5 29 H'003A to H'0
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Section 4 Exception Handling 4.3 H8S/2426, H8S/2426R, H8S/2424 Group Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 15 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 2 ms. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling Vector fetch Prefetch of first Internal processing program instruction (1) (3) φ RES Internal address bus (5) Internal read signal Internal write signal Internal data bus High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Figure 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling Internal processing Vector fetch * φ * Prefetch of first program instruction * RES Address bus (1) (3) (5) RD HWR, LWR D15 to D0 High (2) (4) (6) (1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5)=(2)(4)) (6) First program instruction Note: * Seven program wait states are inserted.
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H8S/2426, H8S/2426R, H8S/2424 Group 4.4 Section 4 Exception Handling Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.
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Section 4 Exception Handling 4.5 H8S/2426, H8S/2426R, H8S/2424 Group Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 5, Interrupt Controller.
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H8S/2426, H8S/2426R, H8S/2424 Group 4.6 Section 4 Exception Handling Trap Instruction Exception Handling Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The values in the program counter (PC), condition code register (CCR), and extended register (EXR) are saved in the stack. 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling 4.7 Illegal Instruction Exception Handling Illegal instruction exception handling starts when the CPU executing an illegal instruction code is detected. Illegal instruction exception handling can be executed at all times in the program execution state. The illegal instruction exception handling is as follows: 1. The values in the PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3.
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H8S/2426, H8S/2426R, H8S/2424 Group 4.8 Section 4 Exception Handling Stack Status after Exception Handling Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal Modes*2 SP EXR Reserved*1 SP CCR CCR CCR*1 CCR*1 PC (16 bits) PC (16 bits) Interrupt control mode 0 Interrupt control mode 2 Advanced Modes SP EXR Reserved*1 SP CCR PC (24 bits) Interrupt control mode 0 CCR PC (24 bits) Interrupt control mode 2 Notes: 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 4 Exception Handling 4.9 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller A block diagram of the interrupt controller is shown in figure 5.1.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.2 Section 5 Interrupt Controller Input/Output Pins Table 5.1 shows the pin configuration of the interrupt controller. Table 5.1 Pin Configuration Name I/O Function NMI Input Nonmaskable external interrupt Rising or falling edge can be selected. IRQ15-A to IRQ0-A* IRQ15-B to IRQ0-B* Note: * Input Maskable external interrupts Rising, falling, or both edges, or level sensing, can be selected. IRQ7-A to IRQ0-A and IRQ7-B to IRQ0-B in the H8S/2424 Group.
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Section 5 Interrupt Controller 5.3 H8S/2426, H8S/2426R, H8S/2424 Group Register Descriptions The interrupt controller has the following registers.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.3.1 Section 5 Interrupt Controller Interrupt Control Register (INTCR) INTCR selects the interrupt control mode, and the detected edge for NMI. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and the initial value should not be changed. 5 INTM1 0 R/W Interrupt Control Select Mode 1 and 0 4 INTM0 0 R/W These bits select either of two interrupt control modes for the interrupt controller.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.3.2 Interrupt Priority Registers A to N (IPRA to IPRN) IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt Sources, Vector Addresses, and Interrupt Priorities).
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved This bit is always read as 0 and the initial value should not be changed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.3.3 IRQ Enable Register (IER) IER controls enabling and disabling of interrupt requests IRQ15 to IRQ0. Bit Bit Name Initial Value R/W Description 15 IRQ15E 0 R/W IRQ15 Enable* The IRQ15 interrupt request is enabled when this bit is 1. 14 IRQ14E 0 R/W IRQ14 Enable* The IRQ14 interrupt request is enabled when this bit is 1. 13 IRQ13E 0 R/W IRQ13 Enable* The IRQ13 interrupt request is enabled when this bit is 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 5 IRQ5E 0 R/W IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. 4 IRQ4E 0 R/W IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. 3 IRQ3E 0 R/W IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. 2 IRQ2E 0 R/W IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCR select the source that generates an interrupt request at pins IRQ15 to IRQ0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ12SCB 0 R/W IRQ12 Sense Control B 8 IRQ12SCA 0 R/W IRQ12 Sense Control A 00: Interrupt request generated at IRQ12 input low level 01: Interrupt request generated at falling edge of IRQ12 input 10: Interrupt request generated at rising edge of IRQ12 input 11: Interrupt request generated at both falling and rising edges of IRQ12 input 7 IRQ11SCB 0 R/W IRQ11 Sense Control B 6
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRQ9SCB 0 R/W IRQ9 Sense Control B 2 IRQ9SCA 0 R/W IRQ9 Sense Control A 00: Interrupt request generated at IRQ9 input low level 01: Interrupt request generated at falling edge of IRQ9 input 10: Interrupt request generated at rising edge of IRQ9 input 11: Interrupt request generated at both falling and rising edges of IRQ9 input 1 IRQ8SCB 0 R/W IRQ8 Sense Control B 0 IRQ8SCA
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller • ISCRL Bit Bit Name Initial Value R/W Description 15 IRQ7SCB 0 R/W IRQ7 Sense Control B 14 IRQ7SCA 0 R/W IRQ7 Sense Control A 00: Interrupt request generated at IRQ7 input low level 01: Interrupt request generated at falling edge of IRQ7 input 10: Interrupt request generated at rising edge of IRQ7 input 11: Interrupt request generated at both falling and rising edges of IRQ7 input 13 IRQ6SCB 0 R/W IRQ6 Sense Control B
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 9 IRQ4SCB 0 R/W IRQ4 Sense Control B 8 IRQ4SCA 0 R/W IRQ4 Sense Control A 00: Interrupt request generated at IRQ4 input low level 01: Interrupt request generated at falling edge of IRQ4 input 10: Interrupt request generated at rising edge of IRQ4 input 11: Interrupt request generated at both falling and rising edges of IRQ4 input 7 IRQ3SCB 0 R/W IRQ3 Sense Control B 6 IRQ3SCA
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 3 IRQ1SCB 0 R/W IRQ1 Sense Control B 2 IRQ1SCA 0 R/W IRQ1 Sense Control A 00: Interrupt request generated at IRQ1 input low level 01: Interrupt request generated at falling edge of IRQ1 input 10: Interrupt request generated at rising edge of IRQ1 input 11: Interrupt request generated at both falling and rising edges of IRQ1 input 1 IRQ0SCB 0 R/W IRQ0 Sense Control B 0 IRQ0SCA
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.3.5 IRQ Status Register (ISR) ISR is an IRQ15 to IRQ0 interrupt request flag register.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.3.6 Section 5 Interrupt Controller IRQ Pin Select Register (ITSR) ITSR selects input pins IRQ15 to IRQ0. • H8S/2426 Group Bit Bit Name Initial Value R/W Description 15 ITS15 0 R/W Selects the IRQ15 input pin. 0: PF2/IRQ15-A selected 1: P27/IRQ15-B selected 14 ITS14 0 R/W Selects the IRQ14 input pin. 0: PF1/IRQ14-A selected 1: P26/IRQ14-B selected 13 ITS13 0 R/W Selects the IRQ13 input pin.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Bit Bit Name Initial Value R/W Description 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: PH2/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin. 0: PA5/IRQ5-A selected 1: P85/IRQ5-B selected 4 ITS4 0 R/W Selects the IRQ4 input pin. 0: PA4/IRQ4-A selected 1: P84/IRQ4-B selected 3 ITS3 0 R/W Selects the IRQ3 input pin.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller • H8S/2424 Group Bit Bit Name 15 to 8 ⎯ Initial Value R/W Description All 0 Reserved R/W The initial value should not be changed. 7 ITS7 0 R/W Selects the IRQ7 input pin. 0: PA7/IRQ7-A selected 1: P47/IRQ7-B selected 6 ITS6 0 R/W Selects the IRQ6 input pin. 0: PA6/IRQ6-A selected 1: P46/IRQ6-B selected 5 ITS5 0 R/W Selects the IRQ5 input pin.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.3.7 Software Standby Release IRQ Enable Register (SSIER) SSIER selects the IRQ pins used to recover from the software standby state. Bit Bit Name Initial Value R/W Description 15 SSI15* 0 R/W Software Standby Release IRQ Setting 14 SSI14* 0 R/W 13 SSI13* 0 R/W These bits select the IRQn pins used to recover from the software standby state.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.4 Interrupt Sources 5.4.1 External Interrupts Section 5 Interrupt Controller The H8S/2426 Group and H8S/2426R Group each have seventeen external interrupts: NMI and IRQ15 to IRQ0. The H8S/2424 Group has nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore the chip from software standby mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller A block diagram of IRQn interrupts is shown in figure 5.2. IRQnE IRQnSCA, IRQnSCB Edge/ level detection circuit IRQn input IRQnF S Q IRQn interrupt request R Clear signal Note: n = 0 to 15 for H8S/2426 Group and H8S/2426R Group, n = 0 to 7 for H8S/2424 Group Figure 5.2 Block Diagram of IRQ Interrupts 5.4.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.5 Section 5 Interrupt Controller Interrupt Exception Handling Vector Table Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. Table 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Interrupt Source ⎯ A/D_0 TPU_0 TPU_1 TPU_2 TPU_3 Origin of Interrupt Source Vector 1 Address* Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation H'0090 IPRF14 to IPRF12 High ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Reserved for 36 system use 37 H'0094 ADI0 38 H'0098 Reserved for 39 system use H'009C IPRF10 to IPRF8 TGI0A 40 H'00A0 TGI0B 41 H'00A4 ⎯ TGI0C 42 H'00A8 ⎯ TGI0D 43 H'00AC TCI0V IPRF6 to IPRF4
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_4 TGI4A 64 H'0100 IPRG6 to IPRG4 High TGI4B 65 H'0104 TCI4V 66 H'0108 ⎯ ⎯ TCI4U 67 H'010C ⎯ ⎯ TGI5A 68 H'0110 TGI5B 69 H'0114 TCI5V 70 H'0118 ⎯ ⎯ TCI5U 71 H'011C ⎯ ⎯ CMIA0 72 H'0120 CMIB0 73 H'0124 OVI0 74 H'0128 Reserved for 75 system use H'012C IPRH14 to IPRH12 CMIA1 76 H'0130
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation SCI_0 ERI0 88 H'0160 IPRI2 to IPRI0 High ⎯ ⎯ RXI0 89 H'0164 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ SCI_1 SCI_2 SCI_3 SCI_4 A/D_1 TXI0 90 H'0168 TEI0 91 H'016C ERI1 92 H'0170 RXI1 93 H'0174 TXI1 94 H'0178 TEI1 95 H'017C ERI2 96 H'0180 RXI2 97 H'0184 ⎯ TXI2 98 H'0188 ⎯ TE
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation IIC2_0 IICI0 116 H'01D0 IPRK6 to IPRK4 High ⎯ ⎯ ⎯ IIC2_1 TPU_6 TPU_7 TPU_8 TPU_9 TPU_10 Reserved for 117 system use H'01D4 ⎯ IICI1 H'01D8 ⎯ ⎯ Reserved for 119 system use H'01DC ⎯ ⎯ TGI6A 120 H'01E0 TGI6B 121 H'01E4 ⎯ TGI6C 122 H'01E8 ⎯ TGI6D 123 H'01EC ⎯ TCI6V
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Vector 1 Address* Interrupt Source Origin of Interrupt Source Vector Number Advanced Mode IPR Priority TPU_11 TGI11A 142 H'0238 IPRM14 to IPRM12 High TGI11B 143 H'023C TCI11V 144 H'0240 ⎯ ⎯ TCI11U 145 H'0244 ⎯ ⎯ Reserved for 146 system use 147 H'0248 ⎯ ⎯ H'024C ⎯ ⎯ 148 H'0250 ⎯ ⎯ 149 H'0254 ⎯ ⎯ 150 H'0258 ⎯ ⎯ 151 H'025C ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DTC Activation DMAC Activation ⎯ ⎯ IPRM
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H8S/2426, H8S/2426R, H8S/2424 Group Interrupt Source ⎯ Origin of Interrupt Source Section 5 Interrupt Controller Vector 1 Address* Vector Number Advanced Mode IPR Priority DTC Activation DMAC Activation Reserved for 170 system use | H'02A8 ⎯ High ⎯ ⎯ | | 255 H'03FC Low ⎯ ⎯ | Notes: 1. Lower 16 bits of the start address. 2. Not supported in the H8S/2424 Group. R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.1 Section 5 Interrupt Controller Interrupt Control Mode 0 In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit of CCR in the CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Program execution status No Interrupt generated? Yes Yes NMI No I=0 No Hold pending Yes IRQ0 Yes No IRQ1 Yes No SSTXI Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Page 138 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.2 Section 5 Interrupt Controller Interrupt Control Mode 2 In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting. Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case. 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Program execution status Interrupt generated? No Yes Yes NMI No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Mask level 5 or below? Level 1 interrupt? No Yes No Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.3 Section 5 Interrupt Controller Interrupt Exception Handling Sequence Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. R01UH0310EJ0500 Rev. 5.
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Page 142 of 1384 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.6.4 Section 5 Interrupt Controller Interrupt Response Times Table 5.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.4 are explained in table 5.5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Symbol Internal Memory 2-State Access 3-State Access 2-State Access 3-State Access Instruction fetch SI 1 4 6+2m 2 3+m Branch address read SJ Stack manipulation SK [Legend] m: Number of wait states in an external device access. 5.6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.7 Usage Notes 5.7.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective after execution of the instruction.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 5 Interrupt Controller 5.7.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.7.
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H8S/2426, H8S/2426R, H8S/2424 Group 5.7.6 Section 5 Interrupt Controller IRQ Status Register (ISR) Depending on the pin status following a reset, IRQnF may be set to 1. Therefore, always read ISR and clear it to 0 after resets. R01UH0310EJ0500 Rev. 5.
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Section 5 Interrupt Controller Page 148 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Section 6 Bus Controller (BSC) This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the bus mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
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Section 6 Bus Controller (BSC) H8S/2426, H8S/2426R, H8S/2424 Group • Idle cycle insertion Idle cycles can be inserted between external read cycles to different areas Idle cycles can be inserted before the write cycle after a read cycle Idle cycles can be inserted before the read cycle after a write cycle • Write buffer function External write cycles and internal accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel • Bus arbitration function I
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H8S/2426, H8S/2426R, H8S/2424 Group EXDMAC address bus*1 Address selector Internal address bus Section 6 Bus Controller (BSC) Area decoder External bus controller Internal bus master bus request signal EXDMAC bus request signal*1 Internal bus master bus acknowledge signal EXDMAC bus acknowledge signal*1 External bus arbiter CS7 to CS0 WAIT BREQ BACK BREQO External bus control signals Internal bus control signals Internal bus controller CPU bus request signal DTC bus request signal DMAC bus reque
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.2 Input/Output Pins Table 6.1 shows the pin configuration of the bus controller. Table 6.1 Pin Configuration Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that normal space is accessed and address output on address bus is enabled. Address hold AH Output Signal indicating the timing for latching the address when the address/data multiplexed I/O space is set.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Name Symbol I/O Function Chip select 4/ row address strobe 4*1/ 2 write enable* CS4/ RAS4*1/ 2 WE* Output Strobe signal indicating that area 4 is selected, DRAM row address strobe signal when area 4 is DRAM space, or write enable signal of the synchronous DRAM when the synchronous DRAM interface is selected.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Name Symbol I/O Function Data transfer acknowledge 1 (DMAC) DACK1 Output Data transfer acknowledge signal for single address transfer by DMAC channel 1. Data transfer acknowledge 0 (DMAC) DACK0 DACK0 Data transfer acknowledge signal for single address transfer by DMAC channel 0. Data transfer acknowledge 3*2 EDACK3*3 Output (EXDMAC) Data transfer acknowledge signal for single address transfer by EXDMAC channel 3.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3 Section 6 Bus Controller (BSC) Register Descriptions The bus controller has the following registers.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.3.1 Bus Width Control Register (ABWCR) ABWCR designates each area in the external address space as either 8-bit access space or 16-bit access space. Bit Bit Name Initial Value* R/W Description 7 ABW7 1/0 R/W Area 7 to 0 Bus Width Control 6 ABW6 1/0 R/W 5 ABW5 1/0 R/W 4 ABW4 1/0 R/W These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.3 Section 6 Bus Controller (BSC) Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH, and WTCRBL) WTCRA and WTCRB select the number of program wait states for each area in the external address space. In addition, CAS latency is set when a synchronous DRAM* is connected. Note: * The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W62 1 R/W Area 6 Wait Control 2 to 0 9 W61 1 R/W 8 W60 1 R/W These bits select the number of program wait states when accessing area 6 while AST6 bit in ASTCR = 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) • WTCRAL Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R Reserved This bit is always read as 0 and cannot be modified. 6 W52 1 R/W Area 5 Wait Control 2 to 0 5 W51 1 R/W 4 W50 1 R/W These bits select the number of program wait states when accessing area 5 while AST5 bit in ASTCR = 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) • WTCRBH Bit Bit Name Initial Value R/W Description 15 ⎯ 0 R Reserved This bit is always read as 0 and cannot be modified. 14 W32 1 R/W Area 3 Wait Control 2 to 0 13 W31 1 R/W 12 W30 1 R/W These bits select the number of program wait states when accessing area 3 while AST3 bit in ASTCR = 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 W22 1 R/W Area 2 Wait Control 2 to 0 9 W21 1 R/W 8 W20 1 R/W These bits select the number of program wait states when accessing area 2 while AST2 bit in ASTCR = 1. A CAS latency is set when the synchronous DRAM* is connected. The setting of area 2 is reflected to the setting of areas 2 to 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) • WTCRBL Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R Reserved This bit is always read as 0 and cannot be modified. 6 W12 1 R/W Area 1 Wait Control 2 to 0 5 W11 1 R/W 4 W10 1 R/W These bits select the number of program wait states when accessing area 1 while AST1 bit in ASTCR = 1.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.4 Section 6 Bus Controller (BSC) Read Strobe Timing Control Register (RDNCR) RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Read Strobe Timing Control 7 to 0 These bits set the negation timing of the read strobe in a corresponding area read access.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ RD RDNn = 0 Data RD RDNn = 1 Data Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space) Page 164 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.5 Section 6 Bus Controller (BSC) CS Assertion Period Control Registers H, L (CSACRH, CSACRL) CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended. Extending the assertion period of the CSn and address signals allows flexible interfacing to external I/O devices.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle Th T1 T2 T3 Tt φ Address CS RD Read Data HWR, LWR Write Data Figure 6.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDNn = 0) Page 166 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.6 Section 6 Bus Controller (BSC) Area 0 Burst ROM Interface Control Register (BROMCRH) Area 1 Burst ROM Interface Control Register (BROMCRL) BROMCRH and BROMCRL are used to make burst ROM interface settings. Area 0 and area 1 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. Bit Bit Name Initial Value R/W Description 7 BSRMn 0 R/W Burst ROM Interface Select Selects the basic bus interface or burst ROM interface.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.3.7 Bus Control Register (BCR) BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. Bit Bit Name Initial Value R/W 15 BRLE 0 R/W Description External Bus Release Enable Enables or disables external bus release.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ICIS0 1 R/W Idle Cycle Insert 0 When an external read cycle and external write cycle are performed consecutively, an idle cycle can be inserted between the bus cycles. 0: Idle cycle not inserted 1: Idle cycle inserted 9 WDBE 0 R/W Write Data Buffer Enable The write data buffer function can be used for an external write cycle or DMAC single address transfer cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) MPXCR is used to make address/data multiplexed I/O interface settings. Bit Bit Name Initial Value R/W Description 7 MPXE 0 R/W Address/Data Multiplexed I/O Interface Enable These bits select the bus interface for areas 6 and 7. 0: Basic bus interface 1: Address/data multiplexed I/O interface 6 to 1 ⎯ All 0 R/W Reserved These bits can be read from or written to.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.9 Section 6 Bus Controller (BSC) DRAM Control Register (DRAMCR) DRAMCR is used to make DRAM/synchronous DRAM interface settings. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. The DRAM interface is not supported by the 5-V version. Bit Bit Name Initial Value R/W Description 15 OEE 0 R/W OE Output Enable The OE signal used when EDO page mode DRAM is connected can be output.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 12 CAST 0 R/W Column Address Output Cycle Number Select Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. 0: Column address output cycle comprises 2 states 1: Column address output cycle comprises 3 states 11 ⎯ 0 R/W Reserved This bit can be read from or written to.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 RMTS2 0 R/W 9 RMTS1 0 R/W DRAM/Continuous Synchronous DRAM Space Select 8 RMTS0 0 R/W These bits designate DRAM/continuous synchronous DRAM space for areas 2 to 5. When continuous DRAM space is set, it is possible to connect large-capacity DRAM exceeding 2 Mbytes per area. In this case, the RAS signal is output from the CS2 pin.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 6 RCDM 0 R/W RAS Down Mode When access to DRAM space is interrupted by an access to normal space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode). The setting of this bit is valid only when the BE bit is set to 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 4 EDDS 0 R/W EXDMAC Single Address Transfer Option Selects whether full access is always performed or burst access is enabled when EXDMAC single address transfer is performed on the DRAM/synchronous DRAM.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W Address Multiplex Select 1 MXC1 0 R/W 0 MXC0 0 R/W These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing. In burst operation on the DRAM/synchronous DRAM interface, these bits also select the row address bits to be used for comparison.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W 011: 11-bit shift 1 MXC1 0 R/W • 0 MXC0 0 R/W When 8-bit access space is designated: Row address bits A23 to A11 used for comparison When 16-bit access space is designated: Row address bits A23 to A12 used for comparison Synchronous DRAM interface 100: 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-b
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 2 MXC2 0 R/W 111: 11-bit shift 1 MXC1 0 R/W • 0 MXC0 0 R/W When 8-bit access space is designated: Row address bits A23 to A11 used for comparison • When 16-bit access space is designated: Row address bits A23 to A12 used for comparison The precharge-sel is A15 to A12 of the column address.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.10 Section 6 Bus Controller (BSC) DRAM Access Control Register (DRACCR) DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. The DRAM interface is not supported by the 5-V version.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 10 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 9 RCD1 0 R/W RAS-CAS Wait Control 8 RCD0 0 R/W These bits select a wait cycle to be inserted between the RAS assert cycle and CAS assert cycle. A 1- to 4-state wait cycle can be inserted.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Precharge-sel Column address Row address Row address RAS SDWCD 0 CAS WE CKE High DQMU, DQML Data bus Address bus PALL ACTV NOP WRIT Tp Tr Tc1 Tc2 Column address Precharge-sel Row address NOP Column address Row address RAS SDWCD 1 CAS WE CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.3.11 Refresh Control Register (REFCR) REFCR specifies DRAM/synchronous DRAM interface refresh control. Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424 Group. The DRAM interface is not supported by the 5-V version. Bit Bit Name Initial Value R/W Description 15 CMF 0 R/(W)* Compare Match Flag Status flag that indicates a match between the values of RTCNT and RTCOR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 11 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0. 10 RTCK2 0 R/W Refresh Counter Clock Select 9 RTCK1 0 R/W 8 RTCK0 0 R/W These bits select the clock to be used to increment the refresh counter. When the input clock is selected with bits RTCK2 to RTCK0, the refresh counter begins counting up.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bit Bit Name Initial Value R/W Description 5 RLW1 0 R/W Refresh Cycle Wait Control 4 RLW0 0 R/W These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle/synchronous DRAM interface autorefresh cycle. This setting applies to all areas designated as DRAM/continuous synchronous DRAM space.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.3.12 Section 6 Bus Controller (BSC) Refresh Timer Counter (RTCNT) RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is started.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.4 Bus Control 6.4.1 Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. In normal mode, a part of area 0, 64-Kbyte address space, is controlled. Figure 6.6 shows an outline of the memory map.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.4.2 Section 6 Bus Controller (BSC) Bus Specifications The external address space bus specifications consist of five elements: bus width, number of access states, number of program wait states, read strobe timing, and chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Table 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.4.
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Section 6 Bus Controller (BSC) (3) H8S/2426, H8S/2426R, H8S/2424 Group Areas 2 to 5 In externally expanded mode, areas 2 to 5 are all external address space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the memory interface of areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS2 to RAS5 signals.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.4.4 Section 6 Bus Controller (BSC) Chip Select Signals This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external space area is accessed. Figure 6.7 shows an example of CS0 to CS7 signals output timing. Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit for the port corresponding to the CS0 to CS7 pins.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus Area n external address CSn Figure 6.7 CSn Signal Output Timing (n = 0 to 7) Page 192 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.5 Section 6 Bus Controller (BSC) Basic Bus Interface The basic bus interface enables direct connection of ROM, SRAM, and so on. 6.5.1 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (2) 16-Bit Access Space Figure 6.9 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.5.2 Section 6 Bus Controller (BSC) Valid Strobes Table 6.3 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.5.3 (1) Basic Timing 8-Bit, 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Notes: 1.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) 8-Bit, 3-State Access Space Figure 6.11 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is always fixed high. Wait states can be inserted. Bus cycle T1 T3 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR High LWR Write D15 to D8 D7 to D0 Valid High impedance Notes: 1. n = 0 to 7 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (3) 16-Bit, 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states cannot be inserted.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T2 T1 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.13 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.14 Bus Timing for 16-Bit, 2-State Access Space (Word Access) Page 200 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 6 Bus Controller (BSC) 16-Bit, 3-State Access Space Figures 6.15 to 6.17 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower half (D7 to D0) for odd addresses. Wait states can be inserted.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.16 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access) Page 202 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 6.17 Bus Timing for 16-Bit, 3-State Access Space (Word Access) R01UH0310EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) 6.5.4 H8S/2426, H8S/2426R, H8S/2424 Group Wait Control When accessing external space, this LSI can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDNn = 0 Figure 6.18 Example of Wait State Insertion Timing 6.5.5 Read Strobe (RD) Timing The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Bus cycle T1 T2 T3 φ Address bus CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus DACK, EDACK Figure 6.19 Example of Read Strobe Timing Page 206 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.5.6 Section 6 Bus Controller (BSC) Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set for individual areas.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0). 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.6.3 Section 6 Bus Controller (BSC) Data Bus The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABW7 and ABW6 bits in ABWCRA. For the 8-bit access space, AD15 to AD8 are valid for both address and data. For the 16-bit access space, AD15 to AD0 are valid for both address and data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read AD15 to AD8 Read data Address HWR Write LWR AD15 to AD8 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.21 Bus Timing for 8-Bit, 2-State Data Access Space Page 210 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) 8-Bit, 3-State Data Access Space Figure 6.22 shows the bus timing for an 8-bit, 3-state data access space. When an 8-bit access space is accessed, the upper halves (AD15 to AD8) of both the address bus and data bus are used. Wait states can be inserted in the data cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (3) 16-Bit, 2-State Data Access Space Figures 6.23 to 6.25 show bus timings for a 16-bit, 2-state data access space. When a 16-bit access space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper half (AD15 to AD8) of the data bus is used for even addresses and the lower half (AD7 to AD0) of the data bus is used for odd addresses. Wait states cannot be inserted in the data cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read AD15 to AD8 Address AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.24 Bus Timing for 16-Bit, 2-State Data Access Space (Odd Address Byte Access) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 φ Address bus CSn AH RD Read AD15 to AD8 Address Read data AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address Write data AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 0 Figure 6.25 Bus Timing for 16-Bit, 2-State Data Access Space (Word Access) Page 214 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 6 Bus Controller (BSC) 16-Bit, 3-State Data Access Space Figures 6.26 to 6.28 show bus timings for a 16-bit, 3-state data access space. When a 16-bit access space is accessed, the entire address bus (AD15 to AD0) is used for all addresses, and the upper half (AD15 to AD8) of the data bus is used for even addresses and the lower half (AD7 to AD0) of the data bus is used for odd addresses. Wait states can be inserted in the data cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read AD15 to AD8 Address AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.27 Bus Timing for 16-Bit, 3-State Data Access Space (Odd Address Byte Access) Page 216 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Address cycle Tma1 Tma2 Data cycle T1 T2 T3 φ Address bus CSn AH RD Read AD15 to AD8 Address Read data AD7 to AD0 Address Read data HWR LWR Write AD15 to AD8 Address Write data AD7 to AD0 Address Write data Notes: 1. n = 6, 7 2. When RDNn = 1 Figure 6.28 Bus Timing for 16-Bit, 3-State Data Access Space (Word Access) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.6.6 (1) Wait Control Address Cycle A single address wait cycle Tmaw can be inserted between Tma1 and Tma2 cycles by setting the ADDEX bit in MPXCR to 1. Figure 6.29 shows the access timing when the address cycle is three cycles.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) Data Cycle In the data cycle, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, refer to section 6.5.4, Wait Control. Wait control settings do not affect the address cycles. 6.6.7 Read Strobe (RD) Timing In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in the basic bus interface.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle In the address/data multiplexed I/O interface, extension cycles can be inserted before and after the data cycle. For details, see section 6.5.6, Extension of Chip Select (CS) Assertion Period. Figure 6.31 shows an example of the timing when the chip select assertion period is extended in the data cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) When consecutively reading from the same area connected to a peripheral LSI whose output floating time is long, data outputs from the peripheral LSI may conflict with address outputs from this LSI. The data conflict can be avoided by inserting the CS assertion period extension cycle after the access cycle. Figure 6.32 shows an example of the operation.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.7 DRAM Interface In this LSI, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to this LSI. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Burst operation is also possible, using fast page mode. Note: The DRAM interface is not supported by the 5-V version. 6.7.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.7.4 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.7.5 Section 6 Bus Controller (BSC) Basic Timing Figure 6.33 shows the basic access timing for DRAM space. The four states of the basic timing consist of one Tp (precharge cycle) state, one Tr (row address output cycle) state, and the Tc1 and two Tc2 (column address output cycle) states.
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Section 6 Bus Controller (BSC) H8S/2426, H8S/2426R, H8S/2424 Group When DRAM space is accessed, the RD signal is output as the OE signal for DRAM. When connecting DRAM provided with an EDO page mode, the OE signal should be connected to the (OE) pin of the DRAM. Setting the OEE bit to 1 in DRAMCR enables the OE signal for DRAM space to be output from a dedicated OE pin.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.7.6 Section 6 Bus Controller (BSC) Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in DRAMCR. Use the setting that gives the optimum specification values (CAS pulse width, etc.) according to the DRAM connected and the operating frequency of this LSI. Figure 6.34 shows an example of the timing when a 3-state column address output cycle is selected.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.7.7 Row Address Output State Control If the RAST bit is set to 1 in DRAMCR, the RAS signal goes low from the beginning of the Tr state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal. Use the optimum setting according to the DRAM connected and the operating frequency of this LSI. Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in DRACCR allows from one to three Trw states, in which row address output is maintained, to be inserted between the Tr cycle, in which the RAS signal goes low, and the Tc1 cycle, in which the column address is output.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.7.8 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one Tp state is always inserted when DRAM space is accessed. From one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the DRAM connected and the operating frequency of this LSI. Figure 6.37 shows the timing when two Tp states are inserted.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.7.9 Section 6 Bus Controller (BSC) Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.38 Example of Wait State Insertion Timing (2-State Column Address Output) Page 232 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Tp Section 6 Bus Controller (BSC) Tr By program wait By WAIT pin Tc1 Tw Tw Tc2 Tc3 φ WAIT Address bus Row address Column address RASn (CSn) UCAS, LCAS Read WE (HWR) High OE (RD) Data bus UCAS, LCAS Write WE (HWR) OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 6.39 Example of Wait State Insertion Timing (3-State Column Address Output) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.7.10 Byte Access Control When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access, and figure 6.41 shows an example of 2-CAS DRAM connection.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration 10-bit column address This LSI (Address shift size set to 10 bits) RASn (CSn) RAS UCAS UCAS LCAS LCAS HWR (WE) RD (OE) A10 WE OE A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A9 to A0 Column address input: A9 to A0 D15 to D0 Figure 6.41 Example of 2-CAS DRAM Connection R01UH0310EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) 6.7.11 H8S/2426, H8S/2426R, H8S/2424 Group Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc1 Tc2 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write High OE (RD) Data bus Note: n = 2 to 5 Figure 6.42 Operation Timing in Fast Page Mode (RAST = 0, CAST = 0) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ Address bus Row address Column address 1 Column address 2 RASn (CSn) UCAS, LCAS WE (HWR) Read High OE (RD) Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 6.43 Operation Timing in Fast Page Mode (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Note, however, that the RAS signal will go high if: ⎯ a refresh operation is initiated in the RAS down state ⎯ self-refreshing is performed ⎯ the chip enters software standby mode ⎯ the external bus is released ⎯ the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) • RAS Up Mode To select RAS up mode, clear the RCDM bit to 0 in DRAMCR. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.45 shows an example of the timing in RAS up mode.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.7.12 Section 6 Bus Controller (BSC) Refresh Control This LSI is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.47 Compare Match Timing TRp TRr TRc1 TRc2 φ CSn (RASn) UCAS, LCAS Figure 6.48 CBR Refresh Timing Page 242 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) A setting can be made in bits RCW1 and RCW0 in REFCR to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 in REFCR to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations. Figure 6.49 shows the timing when bits RCW1 and RCW0 are set. TRp TRrw TRr TRc1 TRc2 φ CSn (RASn) UCAS, CAS Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Depending on the DRAM used, modification of the WE signal may not be permitted during the refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and retains its value prior to the start of the refresh period.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in REFCR. When a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.51.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) In some DRAMs provided with a self-refresh mode, the RAS signal precharge time immediately after self-refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in REFCR to make the precharge time immediately after self-refreshing from 1 to 7 states longer than the normal precharge time.
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H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 6 Bus Controller (BSC) Refreshing and All-Module-Clocks-Stopped Mode In this LSI, if the ACSE bit is set to 1 in MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF, EXMSTPCR = H'FFFF) or for operation of the 8-bit timer module alone (MSTPCR = H'FFFE, EXMSTPCR = H'FFFF), and a transition is made to the sleep state, the all-module-clocks-stopped mode is entered, in which the bus
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tc2 φ Address bus Row address Column address RASn (CSn) UCAS, LCAS WE (HWR) High OE (RD) Read Data bus WE (HWR) Write OE (RD) High Data bus DACK or EDACK Note: n = 2 to 5 Figure 6.53 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 (RAST = 0, CAST = 0) Page 248 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) When DDS = 0 or EDDS = 0 When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing DRAM space. Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.8 Synchronous DRAM Interface In the H8S/2426R Group, external address space areas 2 to 5 can be designated as continuous synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR. Synchronous DRAM of CAS latency 1 to 4 can be connected.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT), and mode-register write (MRS). Commands for bank control cannot be used. 6.8.2 Address Multiplexing With continuous synchronous DRAM space, the row address and column address are multiplexed.
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Section 6 Bus Controller (BSC) 6.8.3 H8S/2426, H8S/2426R, H8S/2424 Group Data Bus If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous DRAM space is set to 1, areas 2 to 5 are designated as 8-bit continuous synchronous DRAM space; if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space. In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be connected directly.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Table 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.8.5 Synchronous DRAM Clock The synchronous clock (SDRAMφ) is output from the CS5 pin. SDRAMφ is shifted by 90° phase from φ. Therefore, a stable margin is ensured for the synchronous DRAM that operates at the rising edge of clocks. Figure 6.55 shows the relationship between φ and SDRAMφ. Tcyc φ 1/4 Tcyc (90°) SDRAMφ Figure 6.55 Relationship between φ and SDRAMφ 6.8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT Figure 6.56 Basic Access Timing of Synchronous DRAM (CAS Latency 1) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.8.7 CAS Latency Control CAS latency is controlled by settings of the W22 to W20 bits of WTCRB. Set the CAS latency count, as shown in table 6.11, by the setting of synchronous DRAM. Depending on the setting, the CAS latency control cycle (Tc1) is inserted. WTCRB can be set regardless of the setting of the AST2 bit of ASTCR. Figure 6.57 shows the CAS latency control timing when synchronous DRAM of CAS latency 3 is connected.
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H8S/2426, H8S/2426R, H8S/2424 Group Tp Section 6 Bus Controller (BSC) Tr Tc1 Tcl1 Tcl2 Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP Figure 6.57 CAS Latency Control Timing (SDWCD = 0, CAS Latency 3) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.8.8 Row Address Output State Control When the command interval specification from the ACTV command to the next READ/WRIT command cannot be satisfied, 1 to 3 states (Trw) that output the NOP command can be inserted between the Tr cycle that outputs the ACTV command and the Tc1 cycle that outputs the column address by setting the RCD1 and RCD0 bits of DRACCR.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.8.9 Section 6 Bus Controller (BSC) Precharge State Count When the interval specification from the PALL command to the next ACTV/REF command cannot be satisfied, from one to four Tp states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of Tp cycles according to the synchronous DRAM connected and the operating frequency of this LSI. Figure 6.59 shows the timing when two Tp states are inserted. R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) The setting of bits TPC1 and TPC0 is also valid for Tp states in refresh cycles. Tp1 Tp2 Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Column address Row address Precharge-sel RAS CAS WE Read CKE High DQMU, DQML Data bus PALL NOP ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL NOP ACTV NOP WRIT NOP Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.8.10 Section 6 Bus Controller (BSC) Bus Cycle Control in Write Cycle By setting the SDWCD bit of the DRACCR to 1, the CAS latency control cycle (Tc1) that is inserted by the WTCRB register in the write access of the synchronous DRAM can be disabled. Disabling the CAS latency control cycle can reduce the write-access cycle count as compared to synchronous DRAM read access. Figure 6.60 shows the write access timing when the CAS latency control cycle is disabled.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.8.11 Byte Access Control When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are used for the control signals needed for byte access. Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of connection of byte control by DQMU and DQML.
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H8S/2426, H8S/2426R, H8S/2424 Group Tp Section 6 Bus Controller (BSC) Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE CKE High DQMU High DQML Upper data bus High impedance Lower data bus PALL ACTV READ NOP Figure 6.62 DQMU and DQML Control Timing (Lower Byte Read Access: CAS Latency 2) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) This LSI (Address shift size set to 8 bits) 16-Mbit synchronous DRAM 1 Mword × 16 bits × 4-bank configuration 8-bit column address CS2 (RAS) RAS CS3 (CAS) CAS CS4 (WE) UCAS (DQMU) LCAS (DQML) CS5 (SDRAMφ) WE DQMU DQML CLK A23 A13 (BS1) A21 A12 (BS0) A12 A11 A11 A10 A10 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 OE (CKE) I/O PORT Row address input: A11 to A0 Column address input:
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H8S/2426, H8S/2426R, H8S/2424 Group 6.8.12 Section 6 Bus Controller (BSC) Burst Operation With synchronous DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, burst access is also provided which can be used when making consecutive accesses to the same row address. This access enables fast access of data by simply changing the column address after the row address has been output.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Column address 1 Row address Tc1 Tcl Tc2 Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Column address 2 Row address Precharge-sel RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP WRIT NOP Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) RAS Down Mode Even when burst operation is selected, it may happen that access to continuous synchronous DRAM space is not continuous, but is interrupted by access to another space. In this case, if the row address active state is held during the access to the other space, the read or write command can be issued without ACTV command generation similarly to DRAM RAS down mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 Continuous synchronous DRAM space read Tc1 Tcl Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP READ NOP Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.8.13 Section 6 Bus Controller (BSC) Refresh Control This LSI is provided with a synchronous DRAM refresh control function. Auto refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as continuous synchronous DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in DRAMCR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) TRp TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.66 Auto Refresh Timing When the interval specification from the PALL command to the REF command cannot be satisfied, setting the RCW1 and RCW0 bits of REFCR enables one to three wait states to be inserted after the TRp cycle that is set by the TPC1 and TPC0 bits of DRACCR.
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H8S/2426, H8S/2426R, H8S/2424 Group TRp1 Section 6 Bus Controller (BSC) TRp2 TRrw TRr TRc1 TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL NOP REF NOP Figure 6.67 Auto Refresh Timing (TPC = 1, TPC0 = 1, RCW1 = 0, RCW0 = 1) When the interval specification from the REF command to the ACTV cannot be satisfied, setting the RLW1 and RLW0 bits of REFCR enables one to three wait states to be inserted in the refresh cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) TRp TRr TRr1 TRcw TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE High PALL REF NOP Figure 6.68 Auto Refresh Timing (TPC = 0, TPC0 = 0, RLW1 = 0, RLW0 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for synchronous DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the synchronous DRAM.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) TRp TRr PALL SELF Software standby TRc2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE CKE NOP Figure 6.69 Self-Refresh Timing (TPC1 = 1, TPC0 = 0, RCW1 = 0, RCW0 = 0, RLW1 = 0, RLW0 = 0) In some synchronous DRAMs provided with a self-refresh mode, the interval between clearing self-refreshing and the next command is specified.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space write Software standby TRc2 TRp1 TRp2 Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE CKE DQMU, DQML Data bus NOP PALL ACTV NOP NOP NOP Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.8.14 Section 6 Bus Controller (BSC) Mode Register Setting of Synchronous DRAM To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After that, access the continuous synchronous DRAM space in bytes.
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Section 6 Bus Controller (BSC) 6.8.15 H8S/2426, H8S/2426R, H8S/2424 Group DMAC and EXDMAC Single Address Transfer Mode and Synchronous DRAM Interface When burst mode is selected on the synchronous DRAM interface, the DACK and EDACK output timing can be selected with the DDS and EDDS bits in DRAMCR. When continuous synchronous DRAM space is accessed in DMAC/EXDMAC single address mode at the same time, these bits select whether or not burst access is to be performed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Column address Row address Tc1 Tcl Tc2 φ SDRAMφ Address bus Precharge-sel Column address Row address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or EDACK Figure 6.72 Example of DACK/EDACK Output Timing when DDS = 1 or EDDS = 1 R01UH0310EJ0500 Rev. 5.
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Section 6 Bus Controller (BSC) H8S/2426, H8S/2426R, H8S/2424 Group When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from the Tr state. In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used when accessing continuous synchronous DRAM space. Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Tp Tr Tc1 Tcl Tc2 φ SDRAMφ Address bus Column address Row address Precharge-sel Row address Column address RAS CAS WE Read CKE High DQMU, DQML Data bus PALL ACTV READ NOP RAS CAS WE Write CKE High DQMU, DQML Data bus PALL ACTV NOP WRIT NOP DACK or RDACK Figure 6.73 Example of DACK/EDACK Output Timing when DDS = 0 or EDDS = 0 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (2) Read Data Extension If the CKSPE bit is set to 1 in DRACCR when the continuous synchronous DRAM space is readaccessed in DMAC/EXDMAC single address mode, the establishment time for the read data can be extended by clock suspend mode. The number of states for insertion of the read data extension cycle (Tsp) is set in bits RDXC1 and RDXC0 in DRACCR. Be sure to set the OEE bit to 1 in DRAMCR when the read data will be extended.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.9 Section 6 Bus Controller (BSC) Burst ROM Interface In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space enables ROM with burst access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.75 Example of Burst ROM Access Timing (ASTn = 1, 2-State Burst Cycle) Page 282 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Full access T1 T2 Burst access T1 T1 φ Upper address bus Lower address bus CSn AS RD Data bus Note: n = 1 and 0 Figure 6.76 Example of Burst ROM Access Timing (ASTn = 0, 1-State Burst Cycle) 6.9.2 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 6.5.4, Wait Control.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.10 Idle Cycle 6.10.1 Operation When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles in the following three cases: (1) when read accesses in different areas occur consecutively, (2) when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 6 Bus Controller (BSC) Write after Read If an external write occurs after an external read while the ICIS0 bit is set to 1 in BCR, an idle cycle is inserted at the start of the write cycle. Figure 6.78 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (3) Read after Write If an external read occurs after an external write while the ICIS2 bit is set to 1 in BCR, an idle cycle is inserted at the start of the read cycle. Figure 6.79 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from an external device.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 6 Bus Controller (BSC) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.80. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (5) Idle Cycle in Case of DRAM Space Access after Normal Space Access In a DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to DRAM space, only a Tp cycle is inserted, and a Ti cycle is not. The timing in this case is shown in figure 6.81.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 DRAM space read Ti Tc1 Tc2 φ Address bus RD RAS UCAS, LCAS Data bus Idle cycle Figure 6.82 Example of Idle Cycle Operation in RAS Down Mode (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) External read DRAM space read Tp Tr Tc1 Tc2 T1 T2 T3 DRAM space write Ti Tc1 Tc2 φ Address bus RD HWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (6) Idle Cycle in Case of Continuous Synchronous DRAM Space Access after Normal Space Access In a continuous synchronous DRAM space access following a normal space access, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC in BCR are valid. However, in the case of consecutive reads in different areas, for example, if the second read is a full access to continuous synchronous DRAM space, only Tp cycle is inserted, and Ti cycle is not.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) In burst access in RAS down mode, the settings of bits ICIS2, ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. However, in read access, note that the timings of DQMU and DQML differ according to the settings of the IDLC bit. The timing in this case is illustrated in figures 6.85 and 6.86. In write access, DQMU and DQML are not in accordance with the settings of the IDLC bit.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space read External space read Tc2 T1 T2 T3 Ti Ti Tc1 TCl Tc2 φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP READ NOP Idle cycle Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl External space read Tc2 T1 T2 T3 Continuous synchronous DRAM space write Ti Tc1 Tc2 TCl φ Address bus Row Column address address Precharge-sel Row address Column address 1 External address Column address 2 External address RAS CAS WE CKE High DQMU, DQML RD HWR, LWR High Data bus PALL ACTV READ NOP WRIT NOP Idle cycle Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (7) Idle Cycle in Case of Normal Space Access after DRAM Space Access Note: The DRAM interface is not supported by the 5-V version. (a) Normal space access after DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after DRAM space access is disabled. Idle cycle insertion after DRAM space access can be enabled by setting the DRMI bit to 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) DRAM space read Tp Tr Tc1 External address space write DRAM space read Tc2 Ti T1 T2 T3 Tc1 Tc2 φ Address bus RD HWR, LWR RAS UCAS, LCAS Data bus Idle cycle Figure 6.89 Example of Idle Cycle Operation after DRAM Access (Write after Read) (IDLC = 0, RAST = 0, CAST = 0) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (b) Normal space access after DRAM space write access While the ICIS2 bit is set to 1 in BCR and a normal space read access occurs after DRAM space write access, idle cycle is inserted in the first read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of the IDLC bit. It does not depend on the DRMI bit in DRACCR. Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group (a) Section 6 Bus Controller (BSC) Normal space access after a continuous synchronous DRAM space read access While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM space read access can be enabled by setting the DRMI bit to 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) (b) Normal space access after a continuous synchronous DRAM space write access If a normal space read cycle occurs after a continuous synchronous DRAM space write access while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is not in accordance with the DRMI bit in DRACCR. Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Table 6.12 shows whether there is an idle cycle insertion or not in the case of mixed accesses to normal space and DRAM space/continuous synchronous DRAM space. Table 6.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Previous Access Next Access ICIS2 ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space write Normal space read 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states inserted 1 DRAM* /continuous 2 synchronous DRAM* space read 1 DRAM* /continuous Normal space read synchronous 2 DRAM* space write 1 DRAM* /continuous 2 synchronous DRAM* space read 0 ⎯ ⎯ ⎯ ⎯ Disabled 1 ⎯ ⎯ ⎯ 0 1 state inserted 1 2 states ins
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Setting the DRMI bit in DRACCR to 1 enables an idle cycle to be inserted in the case of consecutive read and write operations in DRAM/continuous synchronous DRAM space burst access. Figures 6.93 and 6.94 show an example of the timing for idle cycle insertion in the case of consecutive read and write accesses to DRAM/continuous synchronous DRAM space.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Continuous synchronous DRAM space read Tp Tr Tc1 Tcl Continuous synchronous DRAM space write Tc2 Ti Tc1 Tc2 φ Address bus Column Row address address Precharge-sel Row address Column address External address RAS CAS WE CKE High DQMU, DQML Data bus PALL ACTV READ NOP WRIT Idle cycle Figure 6.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.10.2 Section 6 Bus Controller (BSC) Pin States in Idle Cycle Table 6.13 shows the pin states in an idle cycle. Table 6.13 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of following bus cycle D15 to D0 High impedance CSn (n = 7 to 0) High*1 *2 UCAS, LCAS High*2 AS/AH High RD High OE High HWR, LWR High DACKn (n = 1, 0) High EDACKn (n = 3 to 0) High Notes: 1. Remains low in DRAM space RAS down mode. 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) 6.11 Write Data Buffer Function This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit to 1 in BCR. Figure 6.95 shows an example of the timing when the write data buffer function is used.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.12 Section 6 Bus Controller (BSC) Bus Release This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC*1 continue to operate as long as there is no external access. If any of the following requests are issued in the external bus released state, the BREQO signal can be driven low to output a bus request externally.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.12.3 Section 6 Bus Controller (BSC) Transition Timing Figure 6.96 shows the timing for transition to the bus released state. External space access cycle CPU cycle External bus released state T1 T2 φ High impedance Address bus High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO [1] [2] [3] [4] [5] [6] [7] [8] [1] Low level of BREQ signal is sampled at rise of φ.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 6 Bus Controller (BSC) Figure 6.97 shows the timing for transition to the bus released state with the synchronous DRAM interface.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.13 Section 6 Bus Controller (BSC) Bus Arbitration This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration). There are four bus masters⎯the CPU, DTC, DMAC, and EXDMAC*⎯that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
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Section 6 Bus Controller (BSC) 6.13.2 H8S/2426, H8S/2426R, H8S/2424 Group Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can relinquish the bus.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 6 Bus Controller (BSC) EXDMAC The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated. As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in parallel. In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single transfer.
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Section 6 Bus Controller (BSC) H8S/2426, H8S/2426R, H8S/2424 Group 6.15 Usage Notes 6.15.
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H8S/2426, H8S/2426R, H8S/2424 Group 6.15.4 Section 6 Bus Controller (BSC) BREQO Output Timing When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before the BACK signal. This will occur if the next external access request or CBR refresh request occurs while internal bus arbitration is in progress after the chip samples a low level of BREQ. Note: The CBR refreshing control is not supported by the 5-V version. 6.15.
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Section 6 Bus Controller (BSC) Page 314 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Section 7 DMA Controller (DMAC) This LSI has a built-in DMA controller (DMAC), which can carry out data transfer on up to 4 channels. 7.1 Features • Selectable as short address mode or full address mode Short address mode ⎯ Maximum of 4 channels can be used. ⎯ Dual address mode or single address mode can be selected.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) A block diagram of the DMAC is shown in figure 7.1.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.2 Section 7 DMA Controller (DMAC) Input/Output Pins Table 7.1 shows the pin configuration of the interrupt controller. Table 7.
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Section 7 DMA Controller (DMAC) 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 7.2 Section 7 DMA Controller (DMAC) Short Address Mode and Full Address Mode (Channel 0) 0 Short address mode specified (channels 0A and 0B operate independently) MAR_0AH MAR_0BH MAR_0AL Specifies transfer source/transfer destination address IOAR_0A Specifies transfer destination/transfer source address ETCR_0A Specifies number of transfers DMACR_0A MAR_0BL Specifies transfer size, mode, activation source.
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Section 7 DMA Controller (DMAC) 7.3.1 H8S/2426, H8S/2426R, H8S/2424 Group Memory Address Registers (MARA and MARB) MAR is a 32-bit readable/writable register that specifies the source address (transfer source address) or destination address (transfer destination address). MAR consists of two 16-bit registers MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.3.2 Section 7 DMA Controller (DMAC) I/O Address Registers (IOARA and IOARB) IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the source address (transfer source address) or destination address (transfer destination address). The upper 8 bits of the transfer address are automatically set to H'FF.
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Section 7 DMA Controller (DMAC) (1) H8S/2426, H8S/2426R, H8S/2424 Group Short Address Mode The function of ETCR in sequential mode and idle mode differs from that in repeat mode. In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter. ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'00, the DTE bit in DMABCRL is cleared, and transfer ends.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.3.4 Section 7 DMA Controller (DMAC) DMA Control Registers (DMACRA and DMACRB) DMACR controls the operation of each DMAC channel. The DMA has four DMACR registers: DMACR_0A in channel 0 (channel 0A), DMACR_0B in channel 0 (channel 0B), DMACR_1A in channel 1 (channel 1A), and DMACR_1B in channel 1 (channel 1B). In short address mode, channels A and B operate independently, and in full address mode, channels A and B operate together.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 RPE 0 R/W Repeat Enable Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and channel B.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by conversion end interrupt of A/D converter unit 0 Channel B 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled)* 0011: Activated by DREQ pin low-level input* 0100: Activated by SCI channel 0 transmit data emp
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 7 DMA Controller (DMAC) Full Address Mode • DMACR_0A and DMACR_1A Bit Bit Name Initial Value R/W Description 15 DTSZ 0 R/W Data Transfer Size Selects the size of data to be transferred at one time.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 10 to 8 ⎯ All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. [Legend] x: Don't care • DMACR_0B and DMACR_1B Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved This bit can be read from or written to. However, the write value should always be 0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W Data Transfer Factor 3 to 0 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTF3 0 R/W • 2 DTF2 0 R/W 0000: Setting prohibited 1 DTF1 0 R/W 0 DTF0 0 R/W 0001: Activated by A/D converter conversion end interrupt Block Transfer Mode 0010: Activated by DREQ pin falling edge input (detected as a low level in the first transfer after transfer is enabled) 0011: Activated by DREQ pin low-level input 0100: Activated by SCI channel 0 transmit data empty
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H8S/2426, H8S/2426R, H8S/2424 Group 7.3.5 Section 7 DMA Controller (DMAC) DMA Band Control Registers H and L (DMABCRH and DMABCRL) DMABCR controls the operation of each DMAC channel. The bit functions in the DMABCR registers differ according to the transfer mode. (1) Short Address Mode • DMABCRH Bit Bit Name Initial Value R/W Description 15 FAE1 0 R/W Full Address Enable 1 Specifies whether channel 1 is to be used in short address mode or full address mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 11 DTA1B 0 R/W Data Transfer Acknowledge 1B 10 DTA1A 0 R/W Data Transfer Acknowledge 1A 9 DTA0B 0 R/W Data Transfer Acknowledge 0B 8 DTA0A 0 R/W Data Transfer Acknowledge 0A These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTE1B 0 R/W Data Transfer Enable 1B 6 DTE1A 0 R/W Data Transfer Enable 1A 5 DTE0B 0 R/W Data Transfer Enable 0B 4 DTE0A 0 R/W Data Transfer Enable 0A If the DTE bit is cleared to 0 when DTIE = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 3 DTIE1B 0 R/W Data Transfer End Interrupt Enable 1B 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A 1 DTIE0B 0 R/W Data Transfer End Interrupt Enable 0B 0 DTIE0A 0 R/W Data Transfer End Interrupt Enable 0A These bits enable or disable an interrupt to the CPU or DTC when transfer ends.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 13, 12 ⎯ All 0 R/W Reserved These bits can be read from or written to. However, the write value should always be 0. 11 DTA1 0 R/W Data Transfer Acknowledge 1 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 9 DTA0 0 R/W Data Transfer Acknowledge 0 These bits enable or disable clearing when DMA transfer is performed for the internal interrupt source selected by the DTF3 to DTF0 bits in DMACR of channel 0. It the DTA0 bit is set to 1 when DTE0 = 1, the internal interrupt source is cleared automatically by DMA transfer.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) • DMABCRL Bit Bit Name Initial Value R/W Description 7 DTME1 0 R/W Data Transfer Master Enable 1 Together with the DTE1 bit, this bit controls enabling or disabling of data transfer on channel 1. When both the DTME1 bit and DTE1 bit are set to 1, transfer is enabled for channel 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 6 DTE1 0 R/W Data Transfer Enable 1 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 1. When DTE1 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 5 DTME0 0 R/W Data Transfer Master Enable 0 Together with the DTE0 bit, this bit controls enabling or disabling of data transfer on channel 0. When both the DTME0 bit and DTE0 bit are set to 1, transfer is enabled for channel 0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 4 DTE0 0 R/W Data Transfer Enable 0 Enables or disables DMA transfer for the activation source selected by the DTF3 to DTF0 bits in DMACR of channel 0. When DTE0 = 0, data transfer is disabled and the activation source is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Bit Bit Name Initial Value R/W Description 2 DTIE1A 0 R/W Data Transfer End Interrupt Enable 1A Enables or disables an interrupt to the CPU or DTC when transfer ends. If the DTE1 bit is cleared to 1 when DTIE1A = 1, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.3.6 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for the specific channel, to prevent inadvertent rewriting of registers other than those for the channel concerned.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt request, and reactivating channel 0A. The address register and count register areas are set again during the first DTC transfer, then the control register area is set again during the second DTC chain transfer.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) MAR, IOAR, and ETCR can always be written to regardless of the DMAWER settings. When modifying these registers, the channel to be modified should be halted. 7.3.7 DMA Terminal Control Register (DMATCR) DMATCR controls enabling or disabling of output from the DMAC transfer end pin. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.4 Section 7 DMA Controller (DMAC) Activation Sources DMAC activation sources consist of internal interrupt requests, external requests, and autorequests. The DMAC activation sources that can be specified depend on the transfer mode and channel, as shown in table 7.3. Table 7.
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Section 7 DMA Controller (DMAC) 7.4.1 H8S/2426, H8S/2426R, H8S/2424 Group Activation by Internal Interrupt Request An interrupt request selected as a DMAC activation source can also simultaneously generate an interrupt request for the CPU or DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt request, the DMAC accepts the interrupt request independently of the interrupt controller. Consequently, interrupt controller priority settings are irrelevant.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Activation by External Request If an external request (DREQ pin) is specified as a DMAC activation source, the relevant port should be set to input mode in advance*. Level sensing or edge sensing can be used for external requests. External request operation in normal mode of short address mode or full address mode is described below.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Table 7.4 DMAC Transfer Modes Transfer Mode Transfer Source Remarks Short address mode • TPU channel 0 to 5 compare match/input capture A interrupt • Up to 4 channels can operate independently Dual address mode • 1-byte or 1-word transfer for a single transfer request • Specify source and destination addresses to transfer data in two bus cycles.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Transfer Mode Transfer Source Remarks Full address mode • Auto-request • Max.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Sequential mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.5.3 Section 7 DMA Controller (DMAC) Idle Mode Idle mode can be specified by setting the RPE bit in DMACR and DTIE bit in DMABCRL to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.6 summarizes register functions in idle mode. Table 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and data transfer ends.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit in DMABCRL to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRL. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The upper 8 bits of IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B [Legend] Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCRH to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.8 summarizes register functions in single address mode. Table 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.9 illustrates operation in single address mode (when sequential mode is specified). Address T DACK Transfer 1 byte or word transfer performed in response to 1 transfer request Address B [Legend] Address T = L Address B = L + (–1)DTID · (2DTSZ · (N – 1)) Where: L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode Is Specified) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.5.6 Section 7 DMA Controller (DMAC) Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCRH to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after data transfer of a byte or word in response to a single transfer request, and this is executed the number of times specified in ETCRA.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.11 illustrates operation in normal mode. Transfer Address TA Address BB Address BA [Legend] Address TA Address TB Address BA Address BB Where: LA LB N Address TB = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N – 1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N – 1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Page 364 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Transfer requests (activation sources) are external requests and auto-requests. With auto-requests, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-requests, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.5.7 Section 7 DMA Controller (DMAC) Block Transfer Mode In block transfer mode, data transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCRH and the BLKE bit in DMACRA to 1. In block transfer mode, a data transfer of the specified block size is carried out in response to a single transfer request, and this is executed for the number of times specified in ETCRB.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.13 illustrates operation in block transfer mode when MARB is designated as a block area.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.14 illustrates operation in block transfer mode when MARA is designated as a block area.
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Section 7 DMA Controller (DMAC) H8S/2426, H8S/2426R, H8S/2424 Group ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.15 shows the operation flow in block transfer mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmit data empty and receive data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.5.8 Section 7 DMA Controller (DMAC) Basic Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.17. In this example, wordsize transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.9 (1) DMA Transfer (Dual Address Mode) Bus Cycles Short Address Mode Figure 7.18 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 7 DMA Controller (DMAC) Full Address Mode (Cycle Steal Mode) Figure 7.19 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) (3) Full Address Mode (Burst Mode) Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 7 DMA Controller (DMAC) Full Address Mode (Block Transfer Mode) Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ Pin Falling Edge Activation Timing (5) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin falling edge.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (Normal Mode) (6) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.24 shows an example of normal mode transfer activated by the DREQ pin low level.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.25 shows an example of block transfer mode transfer activated by DREQ pin low level.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.10 (1) DMA Transfer (Single Address Mode) Bus Cycles Single Address Mode (Read) Figure 7.26 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.27 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) (2) Single Address Mode (Write) Figure 7.28 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.29 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) (3) DREQ Pin Falling Edge Activation Timing Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.30 shows an example of single address mode transfer activated by the DREQ pin falling edge.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ Pin Low Level Activation Timing (4) Set the DTA bit in DMABCRH to 1 for the channel for which the DREQ pin is selected. Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low level.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) DREQ pin sampling is performed every cycle, with the rising edge of the next φ cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.11 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Figure 7.33 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.12 Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.11 summarizes the priority order for DMAC channels. Table 7.
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H8S/2426, H8S/2426R, H8S/2424 Group DMA read Section 7 DMA Controller (DMAC) DMA write DMA read DMA write DMA read DMA DMA write read φ Address bus RD HWR LWR DMA control Idle Read Channel 0A Idle Write Read Write Idle Read Write Read Request clear Channel 0B Request hold Selection Channel 1 Request hold Nonselection Bus release Channel 0A transfer Request clear Request hold Bus release Selection Channel 0B transfer Request clear Bus release Channel 1 transfer Figure 7.
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Section 7 DMA Controller (DMAC) 7.5.13 H8S/2426, H8S/2426R, H8S/2424 Group Relation between DMAC and External Bus Requests, Refresh Cycles*1, and EXDMAC*2 When the DMAC accesses external space, contention with a refresh cycle*1, EXDMAC cycle*2, or external bus release cycle may arise.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.5.14 Section 7 DMA Controller (DMAC) DMAC and NMI Interrupts When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit in DMABCRLare set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.5.15 Forced Termination of DMAC Operation If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL. Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.5.16 Section 7 DMA Controller (DMAC) Clearing Full Address Mode Figure 7.37 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. [1] Clear both the DTE bit and DTME bit in DMABCRL to 0, or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) 7.6 Interrupt Sources The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.12 shows the interrupt sources and their priority order. Table 7.
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H8S/2426, H8S/2426R, H8S/2424 Group 7.7 (1) Section 7 DMA Controller (DMAC) Usage Notes DMAC Register Access during Operation Except for forced termination of the DMAC, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, DMAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) • If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.40. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control DMA register operation Idle [1] Transfe source Transfer destination Read Write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1].
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H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 7 DMA Controller (DMAC) Write Data Buffer Function When the WDBE bit of BCR in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 7 DMA Controller (DMAC) Notes: 1. Not supported in the H8S/2424 Group. 2. Not supported in the 5-V version. DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.41 Example in which Low Level Is Not Output at TEND Pin Page 404 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group (5) Section 7 DMA Controller (DMAC) Activation by Falling Edge on DREQ Pin DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
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Section 7 DMA Controller (DMAC) (8) H8S/2426, H8S/2426R, H8S/2424 Group Channel Re-Setting To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Section 8 EXDMA Controller (EXDMAC) This LSI has a built-in dual-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory with a DACK (DMA transfer notification) facility. Note: This EXDMAC is not supported by the H8S/2424 Group. 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.1 shows a block diagram of the EXDMAC.
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H8S/2426, H8S/2426R, H8S/2424 Group 8.2 Section 8 EXDMA Controller (EXDMAC) Input/Output Pins Table 8.1 shows the pin configuration of the EXDMAC. Table 8.
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Section 8 EXDMA Controller (EXDMAC) 8.3 H8S/2426, H8S/2426R, H8S/2424 Group Register Descriptions The EXDMAC has the following registers.
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H8S/2426, H8S/2426R, H8S/2424 Group 8.3.2 Section 8 EXDMA Controller (EXDMAC) EXDMA Destination Address Register (EDDAR) EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when a device with DACK is specified as the transfer destination.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) (2) Block Transfer Mode Bit Bit Name Initial Value R/W Description 31 to 24 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 23 to 16 Undefined R/W Block Size These bits specify the block size (number of bytes or number of words) for block transfer. Setting H'01 specifies one as the block, while setting H'00 specifies the maximum block size, that is 256.
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H8S/2426, H8S/2426R, H8S/2424 Group 8.3.4 Section 8 EXDMA Controller (EXDMAC) EXDMA Mode Control Register (EDMDR) EDMDR controls EXDMAC operations. Bit Bit Name Initial Value R/W Description 15 EDA 0 R/(W) EXDMA Active Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto request mode is specified (by bits MDS1 and MDS0), transfer processing begins when this bit is set to 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 14 BEF 0 R/(W)* Block Transfer Error Flag Flag that indicates the occurrence of an error during block transfer. If an NMI interrupt is generated during block transfer, the EXDMAC immediately terminates the EXDMA operation and sets this bit to 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 10 AMS 0 R/W Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, the EDACK pin is valid. 0: Dual address mode 1: Single address mode 9 MDS1 0 R/W Mode Select 1 and 0 8 MDS0 0 R/W These bits specify the activation source, bus mode, and transfer mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 6 IRF 0 R/(W)* Interrupt Request Flag Flag indicating that an interrupt request has occurred and transfer has ended.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 3 DTSIZE 0 R/W Data Transmit Size Specifies the size of data to be transferred. 0: Byte-size 1: Word-size 2 BGUP 0 R/W Bus Give-Up When this bit is set to 1, the bus can be transferred to an internal bus master in burst mode or block transfer mode. This setting is ignored in normal mode and cycle steal mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) 8.3.5 EXDMA Address Control Register (EDACR) EDACR specifies address register incrementing/decrementing and use of the repeat area function. Bit Bit Name Initial Value R/W Description 15 SAT1 0 R/W Source Address Update Mode 14 SAT0 0 R/W These bits specify incrementing/decrementing of the transfer source address (EDSAR).
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 12 SARA4 0 R/W Source Address Repeat Area 11 SARA3 0 R/W 10 SARA2 0 R/W 9 SARA1 0 R/W 8 SARA0 0 R/W These bits specify the source address (EDSAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 7 DAT1 0 R/W Destination Address Update Mode 6 DAT0 0 R/W These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When an external device with DACK is designated as the transfer destination in single address mode, the specification by these bits is ignored.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Bit Bit Name Initial Value R/W Description 4 DARA4 0 R/W Destination Address Repeat Area 3 DARA3 0 R/W 2 DARA2 0 R/W 1 DARA1 0 R/W 0 DARA0 0 R/W These bits specify the destination address (EDDAR) repeat area. The repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. A repeat area size of 2 bytes to 8 Mbytes can be specified.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) 8.4 Operation 8.4.1 Transfer Modes The transfer modes of the EXDMAC are summarized in table 8.2. Table 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) In block transfer mode, a transfer of the specified block size is executed in response to one transfer request. The block size can be from 1 to 256 bytes or words. Within a block, transfer can be performed at the same high speed as in block transfer mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) EXDMA read cycle EXDMA write cycle φ Address bus EDSAR EDDAR RD WR ETEND Figure 8.2 Example of Timing in Dual Address Mode (2) Single Address Mode In single address mode, the EDACK signal is used instead of the source or destination address register to transfer data directly between an external device and external memory.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.3 shows the data flow in single address mode, and figure 8.4 shows an example of the timing. External address bus External data bus Microcomputer External memory EXDMAC External device with DACK EDACK EDREQ Data flow Figure 8.3 Data Flow in Single Address Mode R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Transfer from external memory to external device with DACK EXDMA cycle φ Address bus EDSAR RD Address to external memory space RD signal to external memory space WR EDACK Data output from external memory Data bus ETEND Transfer from external device with DACK to external memory EXDMA cycle φ Address bus EDDAR Address to external memory space RD WR WR signal to external memory space EDACK Data bus Data output from external d
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H8S/2426, H8S/2426R, H8S/2424 Group 8.4.3 (1) Section 8 EXDMA Controller (EXDMAC) DMA Transfer Requests Auto Request Mode In auto request mode, transfer request signals are automatically generated within the EXDMAC in cases where a transfer request signal is not issued from outside, such as in transfer between two memories, or between a peripheral module that is not capable of generating transfer requests and memory. In auto request mode, transfer is started when the EDA bit is set to 1 in EDMDR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) 8.4.4 Bus Modes There are two bus modes: cycle steal mode and burst mode. When the activation source is an auto request, either cycle steal mode or burst mode can be selected. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode In cycle steal mode, the EXDMAC releases the bus at the end of each transfer of a transfer unit (byte, word, or block).
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 8 EXDMA Controller (EXDMAC) Burst Mode In burst mode, once the EXDMAC acquires the bus it continues transferring data, without releasing the bus, until the transfer end condition is satisfied. There is no burst mode in external request mode. In burst mode, once transfer is started it is not interrupted even if there is a transfer request from another channel with higher priority.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) 8.4.5 Transfer Modes There are two transfer modes: normal transfer mode and block transfer mode. When the activation source is an external request, either normal transfer mode or block transfer mode can be selected. When the activation source is an auto request, normal transfer mode is used. (1) Normal Transfer Mode In normal transfer mode, transfer of one transfer unit is processed in response to one transfer request.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 8 EXDMA Controller (EXDMAC) Block Transfer Mode In block transfer mode, the number of bytes or words specified by the block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256 can be specified. During transfer of a block, transfer requests for other higher-priority channels are held pending.
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Section 8 EXDMA Controller (EXDMAC) 8.4.6 H8S/2426, H8S/2426R, H8S/2424 Group Repeat Area Function The EXDMAC has a function for designating a repeat area for source addresses and/or destination addresses. When a repeat area is designated, the address register values repeat within the range specified as the repeat area.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) If the EDA bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 8.9 illustrates the operation of the repeat area function.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure 8.10 shows an example in which block transfer mode is used together with the repeat area function.
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H8S/2426, H8S/2426R, H8S/2424 Group 8.4.7 Section 8 EXDMA Controller (EXDMAC) Registers during DMA Transfer Operation EXDMAC register values are updated as DMA transfer processing is performed. The updated values depend on various settings and the transfer status.
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Section 8 EXDMA Controller (EXDMAC) H8S/2426, H8S/2426R, H8S/2424 Group When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. In a longword access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) When transfer is halted by writing 0 to the EDA bit, the EDA bit remains at 1 during the DMA transfer period. In block transfer mode, since a block-size transfer is carried out without interruption, the EDA bit remains at 1 from the time 0 is written to it until the end of the current block-size transfer. In burst mode, transfer is halted for up to three DMA transfers following the bus cycle in which 0 is written to the EDA bit.
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H8S/2426, H8S/2426R, H8S/2424 Group (5) Section 8 EXDMA Controller (EXDMAC) BEF Bit in EDMDR In block transfer mode, the specified number of transfers (equivalent to the block size) is performed in response to a single transfer request. To ensure that the correct number of transfers is carried out, a block-size transfer is always executed, except in the event of a reset, transition to standby mode, or generation of an NMI interrupt.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) (1) Transfer Requests from Multiple Channels (Except Auto Request Cycle Steal Mode) If transfer requests for different channels are issued during a transfer operation, the highestpriority channel (excluding the currently transferring channel) is selected. The selected channel begins transfer after the currently transferring channel releases the bus.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) The selected channel begins transfer after the currently transferring channel releases the bus. If there is a bus request from a bus master other than the EXDMAC at this time, a cycle for the other bus master is initiated. If there is no other bus request, the bus is released for one cycle. Figure 8.14 shows examples of transfer timing in cases that include auto request cycle steal mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) 8.4.9 (1) EXDMAC Bus Cycles (Dual Address Mode) Normal Transfer Mode (Cycle Steal Mode) Figure 8.15 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. After one byte or word has been transferred, the bus is released.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 8 EXDMA Controller (EXDMAC) Normal Transfer Mode (Burst Mode) Figure 8.16 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space. In burst mode, one-byte or one-word transfers are executed continuously until transfer ends.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) (3) Block Transfer Mode (Cycle Steal Mode) Figure 8.17 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. One block is transferred in response to one transfer request, and after the transfer, the bus is released.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Falling Edge Activation Timing Figure 8.18 shows an example of normal mode transfer activated by the EDREQ pin falling edge.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) One block transfer One block transfer EXDMA read EXDMA write Transfer source Transfer destination Bus release EXDMA read Bus release EXDMA write Bus release φ EDREQ Address bus EXDMA control Idle Read Channel Idle Minimum 3 cycles [2] [3] Idle Request clearance period Request Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Transfer destination Read Write Request clearance period Request [
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H8S/2426, H8S/2426R, H8S/2424 Group (5) Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Low Level Activation Timing Figure 8.20 shows an example of normal mode transfer activated by the EDREQ pin low level.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) One block transfer One block transfer EXDMA read EXDMA write Transfer source Transfer destination Bus release EXDMA read Bus release EXDMA write Bus release φ EDREQ Address bus EXDMA control Idle Read Channel Write Transfer source Read Write Idle Request clearance period Request [2] [3] Minimum 3 cycles [4] Acceptance resumed [1] [2], [5] [3], [6] [4], [7] Idle Request clearance period Request Minimum 3 cycles
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H8S/2426, H8S/2426R, H8S/2424 Group 8.4.10 (1) Section 8 EXDMA Controller (EXDMAC) EXDMAC Bus Cycles (Single Address Mode) Single Address Mode (Read) Figure 8.22 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) EXDMA read EXDMA read EXDMA read φ Address bus RD EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.23 Example of Single Address Mode (Word Read) Transfer After one byte or word has been transferred in response to one transfer request, the bus is released. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. (2) Single Address Mode (Write) Figure 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.25 shows an example of transfer when ETEND output is enabled, and word-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. EXDMA write EXDMA write EXDMA write φ Address bus HWR LWR EDACK ETEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) (3) EDREQ Pin Falling Edge Activation Timing Figure 8.26 shows an example of single address mode transfer activated by the EDREQ pin falling edge.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 8 EXDMA Controller (EXDMAC) EDREQ Pin Low Level Activation Timing Figure 8.27 shows an example of single address mode transfer activated by the EDREQ pin low level.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) 8.4.11 (1) Examples of Operation Timing in Each Mode Auto Request/Cycle Steal Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. There is a one-cycle bus release interval between the end of a one-transfer-unit EXDMA cycle and the start of the next transfer.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU cycle CPU operation External space EXDMA single transfer cycle CPU cycle External space Last transfer cycle EXDMA single transfer cycle CPU cycle EXDMA single transfer cycle External space CPU cycle External space EDACK ETEND Figure 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) (2) Auto Request/Burst Mode/Normal Transfer Mode When the EDA bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. If the BGUP bit is 1 in EDMDR, the bus is transferred in the event of a bus request from another bus master.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) φ pin 1 bus cycle Bus cycle CPU operation CPU cycle CPU cycle External space External space EXDMA read EXDMA write CPU cycle External space 1 bus cycle EXDMA read EXDMA write CPU cycle EXDMA read EXDMA write External space Figure 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) φ pin Last transfer cycle Bus cycle Bus release EXDMA single transfer cycle EXDMA single transfer cycle 1 cycle EXDMA single transfer cycle Other channel EXDMA cycle Bus release Bus release Original channel EDACK Original channel ETEND Other channel transfer request (EDREQ) Figure 8.34 Auto Request/Burst Mode/Normal Transfer Mode (Contention with Another Channel/Single Address Mode) Page 458 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 8 EXDMA Controller (EXDMAC) External Request/Cycle Steal Mode/Normal Transfer Mode In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least two bus cycles are generated before the next EXDMA cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) φ pin EDREQ EDRAK 2 bus cycles Bus cycle CPU cycle CPU cycle CPU cycle External space CPU operation External space External space EXDMA single transfer cycle Last transfer cycle CPU cycle CPU cycle External space External space EXDMA single transfer cycle CPU cycle External space EDACK ETEND Figure 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) φ pin Original channel EDREQ Original channel EDRAK 1 cycle 3 cycles Bus cycle EXDMA transfer cycle Bus release EXDMA read 1 cycle Other channel transfer cycle EXDMA write Bus release EXDMA read EXDMA write Bus release Other channel EDREQ Other channel EDRAK Figure 8.
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Page 462 of 1384 EDA bit ETEND Bus cycle EDRAK EDREQ φ pin 1 Bus release EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA read EXDMA write Repeated EXDMA read 0 EXDMA write Bus release Last transfer cycle Last block Section 8 EXDMA Controller (EXDMAC) H8S/2426, H8S/2426R, H8S/2424 Group Figure 8.
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R01UH0310EJ0500 Rev. 5.00 Sep 25, 2012 ETEND EDACK Bus cycle EDRAK EDREQ φ pin Bus release EXDMA single transfer cycle EXDMA single transfer cycle EXDMA single transfer cycle Last transfer in block Repeated 1-block-size transfer period Bus release 3 cycles EXDMA single transfer cycle Repeated EXDMA single transfer cycle Bus release Last transfer cycle Last block H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.
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Page 464 of 1384 External space CPU operation ETEND EDACK CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space CPU cycle External space EXDMA single transfer cycle Repeated EXDMA single transfer cycle Last transfer in block 1-block-size transfer period CPU cycle External space CPU cycle 2 bus cycles External space EXDMA single transfer cycle Repeated EXDMA single transfer cycle Last transfer in block 1-block-size transfer period CPU cycle Section 8 EXDMA
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R01UH0310EJ0500 Rev. 5.
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Page 466 of 1384 External space External space CPU operation ETEND EDACK CPU cycle CPU cycle Bus cycle EDRAK EDREQ φ pin External space CPU cycle External space EXDMA EXDMA transfer cycle transfer cycle CPU cycle 1 bus cycle External space EXDMA EXDMA transfer cycle transfer cycle CPU cycle 1 bus cycle External space Repeated EXDMA transfer cycle 1-block-size transfer period CPU cycle 1 bus cycle External space EXDMA EXDMA transfer cycle transfer cycle Last transfer in block CPU
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R01UH0310EJ0500 Rev. 5.00 Sep 25, 2012 Other channel EDRAK Other channel EDREQ ETEND Bus cycle EDRAK EDREQ φ pin Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period Bus release Other channel EXDMA cycle Bus release EXDMA read EXDMA write Repeated EXDMA read EXDMA write Last transfer in block 1-block-size transfer period H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) Figure 8.
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Section 8 EXDMA Controller (EXDMAC) 8.4.12 H8S/2426, H8S/2426R, H8S/2424 Group Ending DMA Transfer The operation for ending DMA transfer depends on the transfer end conditions. When DMA transfer ends, the EDA bit in EDMDR changes from 1 to 0, indicating that DMA transfer has ended. (1) Transfer End by 1 → 0 Transition of EDTCR When the value of EDTCR changes from 1 to 0, DMA transfer ends on the corresponding channel and the EDA bit in EDMDR is cleared to 0.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 8 EXDMA Controller (EXDMAC) Transfer Abort by NMI Interrupt DMA transfer is aborted when an NMI interrupt is generated. The EDA bit is cleared to 0 in all channels. In external request mode, DMA transfer is performed for all transfer requests for which EDRAK has been output. In dual address mode, processing is executed for the write cycle following the read cycle. In block transfer mode, operation is aborted even in the middle of a block-size transfer.
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Section 8 EXDMA Controller (EXDMAC) 8.5 H8S/2426, H8S/2426R, H8S/2424 Group Interrupt Sources EXDMAC interrupt sources are a transfer end indicated by the transfer counter, and repeat area overflow interrupts. Table 8.4 shows the interrupt sources and their priority order. Table 8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 8 EXDMA Controller (EXDMAC) The transfer end interrupt can be cleared either by clearing the IRF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the transfer counter and address registers and then setting the EDA bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 8.46.
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Section 8 EXDMA Controller (EXDMAC) 8.6 (1) H8S/2426, H8S/2426R, H8S/2424 Group Usage Notes EXDMAC Register Access during Operation Except for clearing the EDA bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. (2) Module Stop State When the MSTP14 bit is set to 1 in MSTPCRH, the EXDMAC clock stops and the EXDMAC enters the module stop state.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 8 EXDMA Controller (EXDMAC) Activation Source Acceptance At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the EDREQ pin. Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transferenabled state.
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Section 8 EXDMA Controller (EXDMAC) Page 474 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Section 9 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 9.1 shows a block diagram of the DTC. 9.1 Features • Transfer possible over any number of channels • Three transfer modes 1. Normal mode One operation transfers one byte or one word of data. Memory address is incremented or decremented by 1 or 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR and MSTP32 bit in RMMSTPCR must be set to 1 and 0, respectively. A 32-bit bus connects the DTC to the on-chip RAM (1 Kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.2 Section 9 Data Transfer Controller (DTC) Register Descriptions DTC has the following registers. • • • • • • DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) These six registers cannot be directly accessed from the CPU.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Bit Bit Name Initial Value R/W Description 5 DM1 Undefined ⎯ Destination Address Mode 1 and 0 4 DM0 Undefined ⎯ These bits specify a DAR operation after a data transfer.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.2.2 Section 9 Data Transfer Controller (DTC) DTC Mode Register B (MRB) MRB selects the DTC operating mode. Bit Bit Name Initial Value R/W Description 7 CHNE Undefined ⎯ DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. For details, refer to section 9.5.4, Chain Transfer.
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Section 9 Data Transfer Controller (DTC) 9.2.3 H8S/2426, H8S/2426R, H8S/2424 Group DTC Source Address Register (SAR) SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 9.2.4 DTC Destination Address Register (DAR) DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 9.2.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.2.7 Section 9 Data Transfer Controller (DTC) DTC Enable Registers A to I (DTCERA to DTCERI) DTCER which is comprised of registers, DTCERA to DTCERI, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 9.2. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR for reading and writing.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) 9.2.9 DTC Control Register (DTCCR) DTCCR enables or disables DTC activation by software. Bit Bit Name Initial Value R/W Description 7 SWDTE 0 R/W DTC Software Activation Enable Setting this bit to 1 activates the DTC. Only 1 can be written to this bit.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.3 Section 9 Data Transfer Controller (DTC) Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR or DTCCR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Source flag cleared Clear Clear controller DTCER On-chip peripheral modules IRQ interrupt DTVECR DTCCR Interrupt request Selection circuit Select Clear request DTC CPU Interrupt controller Interrupt mask Figure 9.2 Block Diagram of DTC Activation Source Control Page 484 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.4 Section 9 Data Transfer Controller (DTC) Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF). Register information should be located at the address that is multiple of four within the range. Locating the register information in address space is shown in figure 9.3.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) DTC vector address Register information start address Register information Chain transfer Figure 9.4 Correspondence between DTC Vector Address and Register Information Table 9.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* TPU_0 TGI0A 40 H'0450 DTCEC5 TGI0B 41 H'0452 DTCEC4 TGI0C 42 H'0454 DTCEC3 TGI0D 43 H'0456 DTCEC2 TGI1A 48 H'0460 DTCEC1 TGI1B 49 H'0462 DTCEC0 TGI2A 52 H'0468 DTCED7 TGI2B 53 H'046A DTCED6 TGI3A 56 H'0470 DTCED5 TGI3B 57 H'0472 DTCED4 TGI3C 58 H'0474 DTCED3 TGI3D 59 H'0476 DTCED2 TGI4A 64 H
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Vector Number DTC Vector Address DTCE* SCI_3 RXI3 101 H'04CA DTCEF5 TXI3 102 H'04CC DTCEF4 SCI_4 1 RXI4 105 H'04D2 DTCEG3 TXI4 106 H'04D4 DTCEG2 A/D_1 ADI1 112 H'04E0 DTCEG1 TPU_6 TGI6A 120 H'04F0 DTCEG0 TGI6B 121 H'04F2 DTCEH7 TGI6C 122 H'04F4 DTCEH6 TGI6D 123 H'04F6 DTCEH5 TPU_7 TGI7A 125 H'04FA DTCEH4 TGI7B 126 H'04FC DTCEH3 TP
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H8S/2426, H8S/2426R, H8S/2424 Group 9.5 Section 9 Data Transfer Controller (DTC) Operation The DTC stores register information in the on-chip RAM. When activated, the DTC reads register information that is already stored in the on-chip RAM and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to the onchip RAM.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1? Yes No CHNS = 0? Yes Transfer counter = 0 or DISEL = 1? No No Yes Transfer counter = 0? Yes No DISEL = 1? Yes No Clear activation flag Clear DTCER End Interrupt exception handling Figure 9.5 Flowchart of DTC Operation Page 490 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Table 9.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) 9.5.1 Normal Mode In normal mode, one operation transfers one byte or one word of data. Table 9.4 lists the register function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number of transfers has ended, a CPU interrupt can be requested. Table 9.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.5.2 Section 9 Data Transfer Controller (DTC) Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 9.5 lists the register function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers has ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) 9.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 9.6 lists the register function in block transfer mode. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.5.4 Section 9 Data Transfer Controller (DTC) Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 9.9 shows the operation of chain transfer.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) 9.5.5 Interrupt Sources An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) φ DTC activation request DTC request Data transfer Vector read Read Write Read Write Address Transfer information read Transfer information write Figure 9.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) 9.5.7 Number of DTC Execution States Table 9.7 lists execution status for a single DTC data transfer, and table 9.8 shows the number of states required for each execution status. Table 9.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) The number of execution states is calculated from the formula below. Note that Σ means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1).
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Section 9 Data Transfer Controller (DTC) 9.6 Procedures for Using DTC 9.6.1 Activation by Interrupt H8S/2426, H8S/2426R, H8S/2424 Group The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.7 Examples of Use of the DTC 9.7.1 Normal Mode Section 9 Data Transfer Controller (DTC) An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
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Section 9 Data Transfer Controller (DTC) 9.7.2 H8S/2426, H8S/2426R, H8S/2424 Group Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to NDR of the PPG is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.7.3 Section 9 Data Transfer Controller (DTC) Chain Transfer when Counter = 0 By executing a second data transfer, and performing re-setting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-Kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 9.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 9 Data Transfer Controller (DTC) Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 9.13 Chain Transfer when Counter = 0 Page 504 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 9.7.4 Section 9 Data Transfer Controller (DTC) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1.
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Section 9 Data Transfer Controller (DTC) 9.8 Usage Notes 9.8.1 Module Stop Function Setting H8S/2426, H8S/2426R, H8S/2424 Group DTC operation can be disabled or enabled using the module stop control register. The initial setting is for DTC operation to be enabled. Register access is disabled by setting the module stop state. The module stop state cannot be set while the DTC is activated. For details, refer to section 23, Power-Down Modes. 9.8.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Section 10 I/O Ports Table 10.1 summarizes the port functions of the H8S/2426 Group and H8S/2426R Group. Table 10.2 summarizes the port functions of the H8S/2424 Group. The pins of each port also have other functions such as input/output or external interrupt input pins of on-chip peripheral modules.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Table 10.
PAGE 539
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*3 P35/SCK1/ SCL0 ⎯ All output O Mode 3, 7 Port Port 3 Description General I/O port Mode 1 Mode 2 2 Mode 4 1 P35/OE-B* /CKE-B* /SCK1/SCL0 also functioning as SCI I/Os, I2C I/Os, and bus control signal I/Os Port 4 EXPE = 1 SCL0 2 Tolerance* pin functions other than OE-B*2 and CKE-B*1 P34/SCK0/SCK4-A/SDA0 SDA0 P33/RxD1/SCL1
PAGE 540
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Mode 3, 7 Port Description Mode 1 Port 5 General I/O port P53/IRQ3-A/ADTRG0-A also functioning as interrupt inputs, A/D converter inputs, SCI I/Os, PPG outputs, TPU I/Os, TMR I/Os, I2C I/Os, bus control signal I/Os Mode 2 Mode 4 EXPE = 1 EXPE = 0 Schmitt- Input Pull- Open Drain triggered input Pin*3 up MOS Capability Output Capability 5-V IRQ3-A ⎯ All output ⎯ 2 Tolerance* pin functions P52/BACK-B/IRQ2-A/PO4-B/TIOCA4-B/ TMO0-
PAGE 541
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Mode 3, 7 Port Description Mode 1 Mode 2 Port 9 Dedicated input P97/AN15_1 port also functioning as A/D converter analog inputs and D/A converter analog outputs P96/AN14_1 Mode 4 EXPE = 1 EXPE = 0 Schmitt- Input Pull- Open Drain triggered input Pin*3 up MOS Capability Output Capability 5-V ⎯ ⎯ ⎯ ⎯ O All output pin functions other than address outputs ⎯ O All output ⎯ 2 Tolerance* P95/AN13_1/DA3 P94/AN12_1/DA2 P93/AN11_
PAGE 542
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*3 ⎯ O All output ⎯ Mode 3, 7 Port Description Mode 1 Port D General I/O port D15/AD15 PD7 also functioning as data I/Os and address outputs D14/AD14 PD6 D13/AD13 PD5 D12/AD12 PD4 D11/AD11 PD3 D10/AD10 PD2 D9/AD9 PD1 D8/AD8 PD0 PE7/D7/AD7 PE7 PE6/D6/AD6 PE6 PE5/D5/AD5 PE5 PE4/D4/AD4 PE4 PE3/D3/AD3 PE3 PE2/D2/
PAGE 543
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*3 ⎯ ⎯ ⎯ ⎯ Mode 3, 7 Port Description Mode 1 Port F General I/O port PF7/φ PF7/φ PF6/AS/AH PF6 All output pin functions other than AS and AH RD PF5 All output also functioning as interrupt inputs, bus control signal I/Os, SSU I/Os, and A/D converter inputs Mode 2 Mode 4 EXPE = 1 2 Tolerance* pin functions other than RD HW
PAGE 544
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*3 PG6 ⎯ ⎯ All output ⎯ Mode 3, 7 Port Description Mode 1 Port G General I/O port PG6/BREQ-A also functioning as bus control signal I/Os Mode 2 Mode 4 EXPE = 1 2 Tolerance* pin functions PG5/BACK-A PG5 All output pin functions other than BACK-A PG4/BREQO-A PG4 All output pin functions other than BREQO-A PG3/CS3/RAS3*2/CA
PAGE 545
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*3 PH3/IRQ7-B IRQ7-B ⎯ All output ⎯ Mode 3, 7 Port Port H Description General I/O port Mode 1 Mode 2 Mode 4 2 1 EXPE = 1 PH3/CS7/OE-A* /CKE-A* /IRQ7-B also functioning as interrupt inputs and bus control signal I/Os 2 Tolerance* pin functions other than CS7, OEA*2 and CKE-A*1 PH2/CS6/IRQ6-B PH2/IRQ6-B IRQ6-B All output pin
PAGE 546
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Table 10.
PAGE 547
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Mode 3, 7 Port Port 4 Port 5 Mode 2 Mode 4 Open Drain up MOS Capability Output Capability 5-V ⎯ ⎯ ⎯ ⎯ All output pin functions ⎯ Mode 1 General I/O port P47/IRQ7-B/AN7_0 IRQ7-B also functioning as A/D converter analog inputs and interrupt inputs P46/IRQ6-B/AN6_0 IRQ6-B P45/IRQ5-B/AN5_0 IRQ5-B P44/IRQ4-B/AN4_0 IRQ4-B P43/IRQ3-B/AN3_0 IRQ3-B P42/IRQ2-B/AN2_0 IRQ2-B P41/IRQ1-B/AN1_0 IRQ1-B P40/IRQ0-B/AN0_0 IRQ0-B Genera
PAGE 548
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*2 IRQ7-A O All output ⎯ Mode 3, 7 Port Port A Port B Description Mode 1 General I/O port PA7/A23/CS7/ PA7/A23/CS7/IRQ7A/ PA7/IRQ7-A/ also functioning as address outputs, SSU I/Os, SCI I/Os, and bus control signal outputs IRQ7-A/SSO0-B SSO0-B SSO0-B PA6/A22/IRQ6-A/ SSI0-B PA6/A22/IRQ6-A/ SSI0-B PA6/IRQ6-A/ SSI0-B IRQ6-A PA5/
PAGE 549
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*2 ⎯ Ο All output ⎯ Mode 3, 7 Port Port E Port F Description Mode 1 General I/O port PE7/D7/AD7 PE7 also functioning as data I/Os and address outputs PE6/D6/AD6 PE6 PE5/D5/AD5 PE5 PE4/D4/AD4 PE4 PE3/D3/AD3 PE3 PE2/D2/AD2 PE2 PE1/D1/AD1 PE1 General I/O port also functioning as bus control signal I/Os, SSU I/Os, and A/D co
PAGE 550
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Schmitt- Input Pull- Open Drain up MOS Capability Output Capability 5-V EXPE = 0 triggered input Pin*2 PG6 ⎯ ⎯ All output ⎯ Mode 3, 7 Port Description Port G General I/O port also functioning as bus control signal I/Os Mode 1 Mode 2 PG6/BREQ-A Mode 4 EXPE = 1 1 Tolerance* pin functions PG5/BACK-A PG5 All output pin functions other than BACK-A PG4/BREQO-A/CS4 PG4 All output pin functions other than BREQO-A and CS4 PG3/CS3
PAGE 551
H8S/2426, H8S/2426R, H8S/2424 Group 10.1 Section 10 I/O Ports Port 1 Port 1 is an 8-bit I/O port that also has other functions. Port 1 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 1 data direction register (P1DDR) Port 1 data register (P1DR) Port 1 register (PORT1) Port 1 open drain control register (P1ODR) Port function control register 5 (PFCR5) 10.1.
PAGE 552
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.1.2 Port 1 Data Register (P1DR) P1DR stores output data for the port 1 pins. Bit Bit Name Initial Value R/W Description 7 P17DR 0 R/W 6 P16DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W 10.1.3 Port 1 Register (PORT1) PORT1 shows the pin states of port 1.
PAGE 553
H8S/2426, H8S/2426R, H8S/2424 Group 10.1.4 Section 10 I/O Ports Port 1 Open Drain Control Register (P1ODR) P1ODR specifies the output type of each port 1 pin. Bit Bit Name Initial Value R/W Description 7 P17ODR 0 R/W 6 P16ODR 0 R/W 5 P15ODR 0 R/W Setting a P1ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P1ODR bit to 0 makes the corresponding pin a CMOS output pin.
PAGE 554
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.1.5 Pin Functions Port 1 pins also function as the pins for PPG outputs, TPU I/Os, EXDMAC I/Os (H8S/2426 Group, H8S/2426R Group), SSU I/Os, and DMAC I/Os (H8S/2424 Group). The correspondence between the register specification and the pin functions is shown below.
PAGE 555
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) SSU settings (1) in table below (2) in table (4) in table (3) in table below below below 0 ⎯ EDRAKE TPU channel 2 settings (1) in table below ⎯ (2) in table below P17DDR ⎯ 0 1 1 NDER15 ⎯ ⎯ 0 1 TIOCB2 output P17 input P17 output PO15 output Pin function TIOCB2 input* 0*6 0*6 ⎯ ⎯ SCS0-A input*3*7 SCS0-A I/O*5*7 SCS0-A output*4*7 1 2 TCLKD input* Notes: 1.
PAGE 556
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports SSU settings (2) (1) (2) SSUMS (4) (3) (1) 0 1 MSS 0 CSS1 x CSS0 x 0 1 0 1 x SCS input ⎯ SCS input Automatic SCS I/O SCS output ⎯ Pin state 1 x 0 1 x [Legend] x: Don't care ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 19.4 to 19.6.
PAGE 557
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) SSU settings (1) in table below EDRAKE (2) in table below ⎯ 0 TPU channel 2 (1) in table settings below ⎯ (2) in table below P16DDR ⎯ 0 1 1 NDER14 ⎯ ⎯ 0 1 TIOCA2 output P16 input P16 output PO14 output Pin function TIOCA2 input* TPU channel 2 settings MD3 to MD0 IOA3 to IOA0 (2) (1) B'0000, B'01xx (3) in table below ⎯ 0*5 ⎯ SSCK0-A input*3*6 SSCK0-A output*4*6 1 (2) (1) B'001x B'0010 (1
PAGE 558
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports SSU settings (1) (2) (1) SSUMS (3) (1) (2) (1) 0 MSS (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 19.4 to 19.6.
PAGE 559
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 1 settings Section 10 I/O Ports (2) MD3 to MD0 (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care SSU (1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings SSUMS 0
PAGE 560
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P14/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR.
PAGE 561
H8S/2426, H8S/2426R, H8S/2424 Group SSU (1) (2) (1) (2) (1) Section 10 I/O Ports (3) (3) (2) (3) (2) (3) (1) (3) (3) (1) (3) (3) settings 1 SSUMS 0 0 BIDE 0 1* MSS 2 0 TE 1 0 1* 1 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ SSO ⎯ SSO ⎯ SSO SSO SSO SSO SSO SSO ⎯ SSO SSO ⎯ SSO SSO input output input input output output input output output output output output [Legend] ⎯: Not used as the
PAGE 562
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'110 B'110 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOD3 to IOD0 Other than B'xx00 [Legend] x: Don't care • P12/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU chan
PAGE 563
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 0 settings (2) MD3 to MD0 IOC3 to IOC0 Section 10 I/O Ports (1) B'0000 (2) (1) (1) (2) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'101 B'101 Output function ⎯ Output compare output ⎯ PWM*3 mode 1 output PWM mode 2 output ⎯ [Legend] x: Don't care Notes: 1.
PAGE 564
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 0 settings (2) MD3 to MD0 (1) B'0000 (2) (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'010 B'010 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 s
PAGE 565
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 0 settings (2) MD3 to MD0 IOA3 to IOA0 Section 10 I/O Ports (1) B'0000 (2) (1) (1) (2) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'001 B'001 Output function ⎯ Output compare output ⎯ PWM*2 mode 1 output PWM mode 2 output ⎯ [Legend] x: Don't care Notes: 1.
PAGE 566
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P17/PO15/TIOCB2/TCLKD/SCS0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bits TPSC2 to TPSC0 in TCR_0 and TCR_5, bit NDER15 in NDERH of the PPG, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits SCS0S1 and SCS0S0 in PFCR5, and bit P17
PAGE 567
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 2 settings MD3 to MD0 (2) Section 10 I/O Ports (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care SSU settings (2) (1) (2) SSUMS (3) (1) 0 MSS 0 CSS1 x CSS0 x 0 1 SCS input ⎯ SCS input Pin
PAGE 568
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P16/PO14/TIOCA2/SSCK0-A The pin function is switched as shown below according to the combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1 and CCLR0 in TCR_2), bit NDER14 in NDERH of the PPG, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit P16DDR.
PAGE 569
H8S/2426, H8S/2426R, H8S/2424 Group SSU settings (1) Section 10 I/O Ports (2) SSUMS (1) (3) (1) (2) (1) 0 MSS (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 19.4 to 19.6.
PAGE 570
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 1 settings (2) MD3 to MD0 (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care SSU (1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings 1 SSUMS
PAGE 571
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P14/DACK0/PO12/TIOCA1/SSO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, TPU channel 1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1 and CCLR0 in TCR_1), bit NDER12 in NDERH of the PPG, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits SSO0S1 and SSO0S0 in PFCR5, and bit P14DDR.
PAGE 572
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports SSU (1) (2) (1) (2) (1) (3) (3) (2) (3) (2) (3) (1) (3) (3) (1) (3) (3) settings 1 SSUMS 0 0 BIDE 0 1* MSS 2 0 TE 1 0 1 1* 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ SSO ⎯ SSO ⎯ SSO SSO SSO SSO SSO SSO ⎯ SSO SSO ⎯ SSO SSO input input output output input output input output output output output output [Legend] ⎯: Not used as the
PAGE 573
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 0 settings Section 10 I/O Ports (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'110 B'110 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOD3 to IOD0 Other than B'xx00 [Legend] x: Don't care R01UH0310EJ0500 Rev. 5.
PAGE 574
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P12/TEND0/PO10/TIOCC0/TCLKA The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bits CCLR2 to CCLR0 in TCR_0), bits TPSC2 to TPSC0 in TCR_0 to TCR_5, bit NDER10 in NDERH of the PPG, and bit P12DDR.
PAGE 575
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P11/DREQ1/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER9 in NDERH of the PPG, and bit P11DDR.
PAGE 576
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P10/DREQ0/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits CCLR2 to CCLR0 in TCR_0), bit NDER8 in NDERH of the PPG, and bit P10DDR.
PAGE 577
H8S/2426, H8S/2426R, H8S/2424 Group 10.2 Section 10 I/O Ports Port 2 Port 2 is an 8-bit I/O port that also has other functions. Port 2 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 2 data direction register (P2DDR) Port 2 data register (P2DR) Port 2 register (PORT2) Port 2 open drain control register (P2ODR) Port function control register 3 (PFCR3) 10.2.
PAGE 578
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.2.2 Port 2 Data Register (P2DR) P2DR stores output data for the port 2 pins. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 P26DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W 10.2.3 Port 2 Register (PORT2) PORT2 shows the pin states of port 2.
PAGE 579
H8S/2426, H8S/2426R, H8S/2424 Group 10.2.4 Section 10 I/O Ports Port 2 Open Drain Control Register (P2ODR) P2ODR specifies the output type of each port 2 pin. Bit Bit Name Initial Value R/W Description 7 P27ODR 0 R/W 6 P26ODR 0 R/W 5 P25ODR 0 R/W Setting a P2ODR bit to 1 makes the corresponding pin an NMOS open-drain output pin, while clearing a P2ODR bit to 0 makes the corresponding pin a CMOS output pin.
PAGE 580
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.2.5 Pin Functions Port 2 pins also function as the pins for PPG outputs, TPU I/Os, interrupt inputs (H8S/2426 Group, H8S/2426R Group), 8-bit timer I/Os (H8S/2424 Group), I2C I/Os, and bus control signal inputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 581
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 5 settings MD3 to MD0 (2) Section 10 I/O Ports (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P26/PO6/TIOCA5/IRQ14-B/SDA2/ADTRG1 The pin function is switched as shown below according to the combinatio
PAGE 582
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 5 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000, B'01xx (2) (1) (1) (2) B'001x B'0010 B'0011 Other than B'xx00 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 B'xx00 Other than B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'01 B'01 Output function ⎯ Output compare output ⎯ PWM*3 mode 1 output PWM mode 2 output ⎯ [Legend] x: Don't care Notes: 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ WAITE TPU channel 4 settings (1) in table below ⎯ P25DDR 0 0 1 ⎯ ⎯ ⎯ 0 TIOCB4-A output*4 P25 input P25 output PO5-A output*3 NDER5 Pin function (2) in table below TIOCB4-A input*1*4 IRQ13-B interrupt input* 2 Notes: 1. 2. 3. 4. TIOCB4-A input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx. IRQ13-B input when the ITS13 bit in ITSR is 1.
PAGE 584
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P24/IRQ12-B/PO4-A/TIOCA4-A/RxD4-A The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOA3 to IOA0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bit NDER4 in NDERL of the PPG, bit RE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit RXD4S in PFCR4, bit P24DDR, and bit ITS12 in ITSR of the interrupt controller.
PAGE 585
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P23/IRQ11-B/PO3-A/TIOCD3-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS and TPUS in PFCR3, bit TXD4S in PFCR4, bit P23DDR, and bit ITS11 in ITSR of the interrupt controller.
PAGE 586
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P22/IRQ10-B /PO2-A/TIOCC3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P22DDR, and bit ITS10 in ITSR of the interrupt controller.
PAGE 587
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P21/IRQ9-B/PO1-A/TIOCB3-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P21DDR, and bit ITS9 in ITSR of the interrupt controller.
PAGE 588
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P20/PO0-A/TIOCA3-A/IRQ8-B The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS and TPUS in PFCR3, bit P20DDR, and bit ITS8 in ITSR of the interrupt controller.
PAGE 589
H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 10 I/O Ports Pin Functions of H8S/2424 Group • P27/PO7/TIOCB5/SCL2 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOB3 to IOB0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER7 in NDERL of the PPG, bit ICE in ICCRA_2 of the I2C, and bit P27DDR.
PAGE 590
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P26/PO6/TIOCA5/SDA2/ADTRG1 The pin function is switched as shown below according to the combination of the TPU channel 5 settings (by bits MD3 to MD0 in TMDR_5, bits IOA3 to IOA0 in TIOR_5, and bits CCLR1 and CCLR0 in TCR_5), bit NDER6 in NDERL of the PPG, bits TRGS1, TRGS0, and EXTRGS in ADCR_1 of the ADC, bit ICE in ICCRA_2 of the I2C, and bit P26DDR.
PAGE 591
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P25/WAIT-B/PO5-A/TIOCB4-A/TMO1-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, bit WAITS in PFCR4, and bit P25DDR.
PAGE 592
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 4 settings (2) MD3 to MD0 (1) (2) B'0000, B'01xx (2) (1) B'0010 (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P24/PO4-A/TIOCA4-A/TMO0-A/RxD4-A The pin function is switched as shown below according to the combination
PAGE 593
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 3 settings Section 10 I/O Ports (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'110 B'110 Output function ⎯ Output compare output ⎯ PWM*2 mode 1 output PWM mode 2 output ⎯ IOD3 to IOD0 Other than B'xx00 [Legend] x: Don't care Notes: 1. TIOCA4-A input when MD3 to MD0 = B'0000 or B’01xx and IOA3 to IOA0 = B'10xx. 2.
PAGE 594
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P23/PO3-A/TIOCD3-A/TMCI1-A/TxD4-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit TE in SCR_4 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit TXD4S in PFCR4, and bit P23DDR.
PAGE 595
H8S/2426, H8S/2426R, H8S/2424 Group TPU channel 3 settings Section 10 I/O Ports (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'110 B'110 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOD3 to IOD0 Other than B'xx00 [Legend] x: Don't care R01UH0310EJ0500 Rev. 5.
PAGE 596
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P22/PO2-A/TIOCC3-A/TMCI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOC3 to IOC0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER2 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P22DDR.
PAGE 597
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P21/PO1-A/TIOCB3-A/TMRI1-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P21DDR.
PAGE 598
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P20/PO0-A/TIOCA3-A/TMRI0-A The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOA3 to IOA0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER0 in NDERL of the PPG, bits PPGS, TPUS, and TMRS in PFCR3, and bit P20DDR.
PAGE 599
H8S/2426, H8S/2426R, H8S/2424 Group 10.3 Section 10 I/O Ports Port 3 Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 3 data direction register (P3DDR) Port 3 data register (P3DR) Port 3 register (PORT3) Port 3 open drain control register (P3ODR) Port function control register 2 (PFCR2) 10.3.
PAGE 600
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.3.2 Port 3 Data Register (P3DR) P3DR stores output data for the port 3 pins. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W 10.3.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O.
PAGE 601
H8S/2426, H8S/2426R, H8S/2424 Group 10.3.4 Section 10 I/O Ports Port 3 Open Drain Control Register (P3ODR) P3ODR specifies the output type of each port 3 pin. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits.
PAGE 602
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.3.5 Pin Functions Port 3 pins also function as the pins for SCI I/Os, I2C I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 603
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) OEE ⎯ OES ⎯ RMTS2 to RMTS0 ⎯ ICE 0 CKE1 C/A ⎯ 1 ⎯ ⎯ 1 ⎯ ⎯ ⎯ 0 CKE0 0 0 1 ⎯ ⎯ ⎯ ⎯ P35 input P35 output SCK1 output SCK1 output SCK1 input SCL0 I/O*1 P35DDR Pin function 1 1 0 Notes: 1. NMOS open-drain output regardless of P35ODR. 2. Not supported in the H8S/2426 and H8S/2424 Groups. 3. Not supported in the 5-V version.
PAGE 604
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P33/RxD1/SCL1 The pin function is switched as shown below according to the combination of bit ICE in ICCRA_1 of the I2C, bit RE in SCR_1 of the SCI, and bit P33DDR. ICE 0 RE 0 P33DDR Pin function Note: 1 * 1 ⎯ 0 1 ⎯ ⎯ P33 input P33 output RxD1 input SCL1 I/O* NMOS open-drain output regardless of P33ODR.
PAGE 605
H8S/2426, H8S/2426R, H8S/2424 Group 10.4 Section 10 I/O Ports Port 4 Port 4 is an 8-bit input-only port that also has other functions, such as analog input pins. Port 4 has the following register. • Port 4 register (PORT4) 10.4.1 Port 4 Register (PORT4) PORT4 is an 8-bit read-only register that shows the pin states of port 4. PORT4 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P47 ⎯* R The pin states are always read from this register.
PAGE 606
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports (2) Pin Functions of H8S/2424 Group • P47/IRQ7-B/AN7_0 Pin function AN7_0 input IRQ7-B interrupt input* • P46/IRQ6-B/AN6_0 Pin function AN6_0 input IRQ6-B interrupt input* • P45/IRQ5-B/AN5_0 Pin function AN5_0 input IRQ5-B interrupt input* • P44/IRQ4-B/AN4_0 Pin function AN4_0 input IRQ4-B interrupt input* • P43/IRQ3-B/AN3_0 Pin function AN3_0 input IRQ3-B interrupt input* • P42/IRQ2-B/AN2_0 Pin function AN2_0 input IRQ2-B interrupt inp
PAGE 607
H8S/2426, H8S/2426R, H8S/2424 Group 10.5 Section 10 I/O Ports Port 5 Port 5 is a 4-bit I/O port. Port 5 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 5 data direction register (P5DDR) Port 5 data register (P5DR) Port 5 register (PORT5) Port 5 open drain control register (P5ODR) Port function control register 4 (PFCR4) 10.5.
PAGE 608
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.5.3 Port 5 Register (PORT5) PORT5 shows the pin states of port 5. PORT5 cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ Undefined R Reserved If these bits are read, they will return an undefined value. 3 P53 ⎯* R 2 P52 ⎯* R 1 P51 ⎯* R 0 P50 ⎯* R Note: * 10.5.4 If the P53 to P50 bits are read while a P5DDR bit is set to 1, the corresponding P5DR value is read.
PAGE 609
H8S/2426, H8S/2426R, H8S/2424 Group 10.5.5 Section 10 I/O Ports Pin Functions Port 5 pins also function as the pins for SCI I/Os, A/D converter inputs, interrupt inputs, I2C I/Os, bus control signal I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below.
PAGE 610
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P52/SCK2/IRQ2-A/BACK-B/PO4-B/TIOCA4-B/TMO0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bits OS3 to OS0 in TCSR0 of 8-bit timer, bits MD3 to MD0 in TMDR_4 of TPU, bits IOA3 to IOA0 in TIOR_4, TPU channel 4 settings by bits CCLR1 and CCLR0 in TCR_4, bit NDER4 in NDERL of PPG, bit C/A in SMR_2 and bits CKE0 and CKE1 in SCR_2 of the SCI, bits PPGS, T
PAGE 611
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ BRLE BACKS TPU channel (1) in table 4 settings below (2) in table below OS3 to OS0 ⎯ CKE1 ⎯ C/A ⎯ CKE0 ⎯ P52DDR ⎯ 0 1 1 ⎯ ⎯ ⎯ ⎯ NDER4 ⎯ ⎯ 0 1 ⎯ ⎯ ⎯ ⎯ TIOCA4-B 5 output* P52 input P52 output PO4-B 4 output* SCK2 output SCK2 output SCK2 input TMO0-B 6 output* Pin function All 0 Not all 0 1 ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 1 1 5 TIOCA4-B input* * IRQ2-A interrupt input* 2 TPU channel 4
PAGE 612
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P51/RxD2/IRQ1-A/SCL3/BREQ-B/PO2-B/TIOCC3-B/TMCI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit ICE in ICCRA_3 of the I 2 C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOC3 to IOC0 in TIORL_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER2 in NDERL of PPG, bit RE in SCR_2 of the SCI, bit P51DDR, bits PPGS, TPUS, and TMRS in PFCR3,
PAGE 613
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ BRLE BREQS ICE TPU channel 3 settings 0 (1) in table below 1 RE ⎯ P51DDR ⎯ 0 1 1 NDER2 ⎯ ⎯ 0 1 Pin function ⎯ (2) in table below 0 TIOCC3-B output*7 P51 input P51 output PO2-B output* 6 1 ⎯ ⎯ ⎯ ⎯ ⎯ RxD2 input SCL3 I/O*5 TIOCC3-B input*1*7 IRQ1-A interrupt input*2 3 8 TMCI0-B input* * TPU channel 3 settings (2) MD3 to MD0 IOC3 to IOC0 (1) B'0000 (2) (1) B'001x B'0010 B'0011 Other tha
PAGE 614
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P50/TxD2/IRQ0-A/SDA3/BREQO-B/PO0-B/TIOCA3-B/TMRI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE of the bus controller, bit BREQOE, bit ICE in ICCRA_3 of the I2C, bits MD3 to MD0 in TMDR_3 of TPU, bits IOA3 to IOA0 in TIORH_3, TPU channel 3 settings by bits CCLR2 to CCLR0 in TCR_3, bit NDER0 in NDERL of PPG, bit TE in SCR_2 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, bit BRE
PAGE 615
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) BRLE ⎯ BREQOE ⎯ BREQOS ⎯ ICE TPU channel 3 settings (1) in table below 0 1 (2) in table below ⎯ TE ⎯ P50DDR ⎯ 0 1 1 ⎯ ⎯ NDER0 ⎯ ⎯ 0 1 ⎯ ⎯ TIOCA3-B output*7 P50 input P50 output PO0-B output*6 TxD2 output SDA3*5 I/O Pin function 0 ⎯ 1 TIOCA3-B input*1*7 IRQ0-A interrupt input*2 TMRI0-B input*3*8 TPU channel 3 settings (2) MD3 to MD0 IOA3 to IOA0 (1) B'0000 (2) (1) B'001x B'0010
PAGE 616
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.6 Port 6 Note: Port 6 is not supported in the H8S/2424 Group. Port 6 is a 6-bit I/O port that also has other functions. Port 6 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 6 data direction register (P6DDR) Port 6 data register (P6DR) Port 6 register (PORT6) Port 6 open drain control register (P6ODR) Port function control register 3 (PFCR3) 10.6.
PAGE 617
H8S/2426, H8S/2426R, H8S/2424 Group 10.6.2 Section 10 I/O Ports Port 6 Data Register (P6DR) P6DR stores output data for the port 6 pins. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W 10.6.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O.
PAGE 618
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.6.4 Port 6 Open Drain Control Register (P6ODR) P6ODR specifies the output type of each port 6 pin. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits. 5 P65ODR 0 R/W 4 P64ODR 0 R/W 3 P63ODR 0 R/W 2 P62ODR 0 R/W 1 P61ODR 0 R/W 0 P60ODR 0 R/W 10.6.
PAGE 619
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P64/IRQ12-A/DACK0/TMO0-A The pin function is switched as shown below according to the combination of bit SAE0 in DMABCRH of the DMAC, bits OS3 to OS0 in TCSR_0 of the 8-bit timer, bit TMRS in PFCR3, bit P64DDR, and bit ITS12 in ITSR of the interrupt controller. SAE0 0 OS3 to OS0 All 0 P64DDR Pin function 0 ⎯ Not all 0 ⎯ 1 P64 input 1 P64 output ⎯ DACK0 output 2 TMO0-A output* IRQ12-A interrupt input* 1 Notes: 1.
PAGE 620
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P62/IRQ10-A/TEND0/TMCI0-A The pin function is switched as shown below according to the combination of bit TEE0 in DMATCR of the DMAC, bit TMRS in PFCR3, bit P62DDR, and bit ITS10 in ITSR of the interrupt controller. TEE0 P62DDR Pin function 0 1 0 1 P62 input P62 output ⎯ TEND0 output IRQ10-A interrupt input* 1 2 3 TMCI0-A input* * Notes: 1. IRQ10-A input when the ITS10 bit in ITSR is 0. 2.
PAGE 621
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P60/IRQ8-A/DREQ0/TMRI0-A The pin function is switched as shown below according to the combination of bit TMRS in PFCR3, bit P60DDR, and bit ITS8 in ITSR of the interrupt controller. P60DDR Pin function 0 1 P60 input P60 output 1 3. TMRI0-A input* * DREQ0 input IRQ8-A interrupt input* 2 Notes: 1. When used as the counter reset input pin for the TMR, both the CCLR1 and CCLR0 bits in TCR_0 should be set to 1. 2.
PAGE 622
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.7 Port 8 Port 8 is a 6-bit I/O port that also has other functions. Port 8 has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers. • • • • • Port 8 data direction register (P8DDR) Port 8 data register (P8DR) Port 8 register (PORT8) Port 8 open drain control register (P8ODR) Port function control register 3 (PFCR3) 10.7.
PAGE 623
H8S/2426, H8S/2426R, H8S/2424 Group 10.7.2 Section 10 I/O Ports Port 8 Data Register (P8DR) P8DR stores output data for the port 8 pins. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 5 P85DR 0 R/W 4 P84DR 0 R/W 3 P83DR 0 R/W 2 P82DR 0 R/W 1 P81DR 0 R/W 0 P80DR 0 R/W 10.7.3 Output data for a pin is stored when the pin function is specified as a general purpose I/O.
PAGE 624
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.7.4 Port 8 Open Drain Control Register (P8ODR) P8ODR specifies the output type of each port 8 pin. Bit Bit Name Initial Value R/W Description 7, 6 ⎯ All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits.
PAGE 625
H8S/2426, H8S/2426R, H8S/2424 Group 10.7.5 Section 10 I/O Ports Pin Functions Port 8 pins also function as SCI I/Os, interrupt inputs, EXDMAC I/Os, PPG outputs, TPU I/Os, and 8-bit timer I/Os. The correspondence between the register specification and the pin functions is shown below.
PAGE 626
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) TPU channel 4 settings (1) in table below OS3 to OS0 ⎯ All 0 Not all 0 AMS ⎯ ⎯ ⎯ CKE1 ⎯ C/A ⎯ CKE0 ⎯ P85DDR ⎯ 0 1 NDER5 ⎯ ⎯ TIOCB4-B 4 output* P85 input Pin function (2) in table below 1 ⎯ 1 ⎯ ⎯ 1 ⎯ ⎯ ⎯ 1 ⎯ ⎯ ⎯ ⎯ 0 1 ⎯ ⎯ ⎯ ⎯ P85 output PO5-B 3 output* SCK3 output SCK3 output SCK3 input TMO1-B 5 output* 0 0 0 2 4 TIOCB4-B input* * IRQ5-B interrupt input* 1 IRQ5-B inpu
PAGE 627
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P84/IRQ4-B/EDACK2 The pin function is switched as shown below according to the combination of bit AMS in EDMDR_2 of the EXDMAC, bit P84DDR, and bit ITS4 in ITSR of the interrupt controller. Operating mode 1, 2, 4 AMS 3, 7 (EXPE = 1) 0 ⎯ 1 0 1 ⎯ 0 1 P84 input P84 output EDACK2 output P84 input P84 output P84DDR Pin function 3, 7 (EXPE = 0) IRQ4-B interrupt input* Note: * IRQ4-B input when the ITS4 bit in ITSR is 1.
PAGE 628
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) TPU channel 3 settings (1) in table below (2) in table below ETENDE ⎯ RE ⎯ P83DDR ⎯ 0 NDER3 ⎯ ⎯ Pin function 0 1 0 TIOCD3-B output*5 P83 input ⎯ 1 ⎯ 1 0 ⎯ 1 P83 output PO3-B output* 2 4 RxD3 input 5 TIOCD3-B input* * IRQ3-B interrupt input*1 3 6 TMCI1-B input* * Notes: 1. IRQ3-B input when the ITS3 bit in ITSR is 1. 2. TIOCD3-B input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx. 3.
PAGE 629
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P82/IRQ2-B/ETEND2 The pin function is switched as shown below according to the combination of bit ETENDE in EDMDR_2 of the EXDMAC, bit P82DDR, and bit ITS2 in ITSR of the interrupt controller. Operating mode 1, 2, 4 ETENDE 3, 7 (EXPE = 1) 3, 7 (EXPE = 0) 0 0 1 ⎯ 0 1 P82 input P82 output ETEND2 output P82 input P82 output P82DDR Pin function ⎯ 1 IRQ2-B interrupt input* Note: * IRQ2-B input when the ITS2 bit in ITSR is 1.
PAGE 630
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 3 settings (2) MD3 to MD0 (1) B'0000 (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR2 to CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'010 B'010 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care • P80/IRQ0-B/EDREQ2 The pin function is switched as shown below according to the combination of bit P80DDR and b
PAGE 631
H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 10 I/O Ports Pin Functions of H8S/2424 Group • P85/SCK3/PO5-B/TIOCB4-B/TMO1-B The pin function is switched as shown below according to the combination of the TPU channel 4 settings (by bits MD3 to MD0 in TMDR_4, bits IOB3 to IOB0 in TIOR_4, and bits CCLR1 and CCLR0 in TCR_4), bits OS3 to OS0 in TCSR_1 of the 8-bit timer, bit NDER5 in NDERL of the PPG, bit C/A in SMR_3 and bits CKE0 and CKE1 in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P
PAGE 632
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports TPU channel 4 settings MD3 to MD0 (2) (1) B'0000, B'01xx (2) (2) B'0010 (1) (2) B'0011 B'0000, B'0100, B'1xxx B'0001 to B'0011, B'0101 to B'0111 ⎯ B'xx00 CCLR1, CCLR0 ⎯ ⎯ ⎯ ⎯ Other than B'10 B'10 Output function ⎯ Output compare output ⎯ ⎯ PWM mode 2 output ⎯ IOB3 to IOB0 Other than B'xx00 [Legend] x: Don't care Page 602 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 633
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P83/PO3-B/TIOCD3-B/TMCI1-B/RxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOD3 to IOD0 in TIORL_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER3 in NDERL of the PPG, bit RE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P83DDR.
PAGE 634
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • P81/PO1-B/TIOCB3-B/TMRI1-B/TxD3 The pin function is switched as shown below according to the combination of the TPU channel 3 settings (by bits MD3 to MD0 in TMDR_3, bits IOB3 to IOB0 in TIORH_3, and bits CCLR2 to CCLR0 in TCR_3), bit NDER1 in NDERL of the PPG, bit TE in SCR_3 of the SCI, bits PPGS, TPUS, and TMRS in PFCR3, and bit P81DDR.
PAGE 635
H8S/2426, H8S/2426R, H8S/2424 Group 10.8 Section 10 I/O Ports Port 9 Port 9 is an 8-bit input-only port that also has other functions. Port 9 has the following register. • Port 9 register (PORT9) 10.8.1 Port 9 Register (PORT9) PORT9 is an 8-bit read-only register that shows the pin states of port 9. PORT9 cannot be modified. Bit Bit Name Initial Value R/W Description 7 P97 ⎯* R 6 P96 ⎯* R 5 P95 ⎯* The pin states are always read from this register.
PAGE 636
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.8.2 Pin Functions Port 9 also functions as the pins for A/D converter analog inputs and D/A converter analog outputs. The correspondence between pins is as follows.
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H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 10 I/O Ports Pin Functions of H8S/2424 Group • P95/AN13_1/DA3 Pin function AN13_1 input DA3 output • P94/AN12_1/DA2 Pin function AN12_1 input DA2 output R01UH0310EJ0500 Rev. 5.
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Section 10 I/O Ports 10.9 H8S/2426, H8S/2426R, H8S/2424 Group Port A Port A is an 8-bit I/O port that also has other functions. Port A has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.
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H8S/2426, H8S/2426R, H8S/2424 Group 10.9.1 Section 10 I/O Ports Port A Data Direction Register (PADDR) The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. Bit Bit Name Initial Value R/W Description 7 PA7DDR 0 W 6 PA6DDR 0 W Pins PA4 to PA0 are address outputs.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description • Mode 4 Modes 3 and 7 (EXPE = 1) For pins PA6 to PA0, when the corresponding bit of A22E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding pin an address output, while clearing the bit to 0 makes the corresponding pin an input port. Clearing one of bits A22E to A16E to 0 makes the corresponding pin an I/O port, and its function can be switched with PADDR.
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H8S/2426, H8S/2426R, H8S/2424 Group 10.9.2 Section 10 I/O Ports Port A Data Register (PADR) PADR stores output data for the port A pins. Bit Bit Name Initial Value R/W Description 7 PA7DR 0 R/W 6 PA6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W 10.9.3 Port A Register (PORTA) PORTA shows the pin states of port A.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.9.4 Port A Pull-Up MOS Control Register (PAPCR) PAPCR controls on/off of the input pull-up MOS for port A. Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PA7PCR 0 R/W 6 PA6PCR 0 R/W When in an input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 643
H8S/2426, H8S/2426R, H8S/2424 Group 10.9.6 Section 10 I/O Ports Pin Functions Port A pins also function as the pins for address outputs, interrupt inputs, SSU I/Os, SCI I/Os, and bus control signal outputs. The correspondence between the register specification and the pin functions is shown below.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ A23E 6 CS7E* 0 SSU settings (1) in table below PA7DDR 0 Pin function (2) in table below 1 PA7 input 0* ⎯ 2 PA7 output (3) in table below 4 5 SSO0-B output*3*5 SSO0-B input* * IRQ7-A interrupt input* 1 Notes: 1. IRQ7-A input when the ITS7 bit in ITSR is 0. 2. When using as SSO0-B input, set SSO0S1 and SSO0S0 in PFCR5 to B'01 before other register setting. 3.
PAGE 645
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PA6/A22/IRQ6-A/SSI0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of SSU, bit A22E in PFCR1, bits SSI0S1 and SSI0S0 in PFCR5, bit PA6DDR, and bit ITS6 in ITSR of the interrupt controller.
PAGE 646
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports SSU (1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings 1 SSUMS 0 0 BIDE 0 1* MSS 2 0 TE 1 0 1 1* 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ ⎯ SSI SSI SSI ⎯ SSI ⎯ ⎯ ⎯ ⎯ SSI ⎯ SSI SSI ⎯ SSI input input output output input input input input [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port).
PAGE 647
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 EXPE 1 A21E SSU settings PA5DDR Pin function 0 0 (1) in table below 0 PA5 output ⎯ ⎯ (2) in (3) in table table table table below below below below 0*4 ⎯ 0*4 ⎯ 1 PA5 input ⎯ 1 0 SSCK0-B SSCK0-B PA5 input input*2*5 output*3*5 (1) in table below 1 0 A21 PA5 input (2) in 1 output (3) in PA5 SSCK0-B SSCK0-B output input*2*5 output*3*5 IRQ5-A interrupt input* 1 Notes: 1.
PAGE 648
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PA4/A20/IRQ4-A/SCS0-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bit A20E in PFCR1, bit PA4DDR, and bit ITS4 in ITSR of the interrupt controller.
PAGE 649
H8S/2426, H8S/2426R, H8S/2424 Group SSU settings (2) Section 10 I/O Ports (1) (2) SSUMS (4) (3) 0 (1) 1 MSS 0 CSS1 x CSS0 x 0 1 0 1 x SCS input ⎯ SCS input Automatic SCS I/O SCS output ⎯ Pin state 1 x 0 1 x [Legend] x: Don't care ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 19.4 to 19.6. R01UH0310EJ0500 Rev. 5.
PAGE 650
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PA3/A19/SCK4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit C/A in SMR_4 and bits CKE0 and CKE1 in SCR_4 of the SCI, bit A19E in PFCR1, bit SCK4S in PFCR4, and bit PA3DDR.
PAGE 651
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PA2/A18/RxD4-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit RE in SCR_4 of the SCI, bit A18E in PFCR1, bit RXD4S in PFCR4, and bit PA2DDR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PA0/A16 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit A16E in PFCR1, and bit PA0DDR. Operating mode 1, 2 4 EXPE ⎯ ⎯ A16E ⎯ PA0DDR ⎯ Pin function 10.9.
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H8S/2426, H8S/2426R, H8S/2424 Group 10.10 Section 10 I/O Ports Port B Port B is an 8-bit I/O port that also has other functions. Port B has the following registers. • • • • • Port B data direction register (PBDDR) Port B data register (PBDR) Port B register (PORTB) Port B pull-up MOS control register (PBPCR) Port B open drain control register (PBODR) 10.10.1 Port B Data Direction Register (PBDDR) The individual bits of PBDDR specify input or output for the pins of port B.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.10.2 Port B Data Register (PBDR) PBDR stores output data for the port B pins. Bit Bit Name Initial Value R/W Description 7 PB7DR 0 R/W 6 PB6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W 10.10.3 Port B Register (PORTB) PORTB shows the pin states of port B.
PAGE 655
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.10.4 Port B Pull-Up MOS Control Register (PBPCR) PBPCR controls on/off of the input pull-up MOS for port B. PBPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PB7PCR 0 R/W 6 PB6PCR 0 R/W When in a input port register state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 656
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.10.6 Pin Functions Port B pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 657
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB6/A14/TIOCA8 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 8 settings (by bits MD3 to MD0 in TMDR_8, bits IOA3 to IOA0 in TIOR_8, and bits CCLR1 and CCLR0 in TCR_8), and bit PB6DDR.
PAGE 658
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB5/A13/TIOCB7/TCLKG The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOB3 to IOB0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), bits TPSC2 to TPSC0 in TCR_6, TCR_8, TCR_10, and TCR_11, and bit PB5DDR.
PAGE 659
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB4/A12/TIOCA7 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 7 settings (by bits MD3 to MD0 in TMDR_7, bits IOA3 to IOA0 in TIOR_7, and bits CCLR1 and CCLR0 in TCR_7), and bit PB4DDR.
PAGE 660
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB3/A11/TIOCD6/TCLKF The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOD3 to IOD0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_8, and bit PB3DDR.
PAGE 661
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB2/A10/TIOCC6/TCLKE The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOC3 to IOC0 in TIORL_6, and bits CCLR2 to CCLR0 in TCR_6), bits TPSC2 to TPSC0 in TCR_6 to TCR_11, and bit PB2DDR.
PAGE 662
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB1/A9/TIOCB6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOB3 to IOB0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB1DDR.
PAGE 663
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PB0/A8/TIOCA6 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 6 settings (by bits MD3 to MD0 in TMDR_6, bits IOA3 to IOA0 in TIORH_6, and bits CCLR2 to CCLR0 in TCR_6), and bit PB0DDR.
PAGE 664
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.10.7 Port B Input Pull-Up MOS States Port B has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3, 4, and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3, 4, and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.
PAGE 665
H8S/2426, H8S/2426R, H8S/2424 Group 10.11 Section 10 I/O Ports Port C Port C is an 8-bit I/O port that also has other functions. Port C has the following registers. • • • • • Port C data direction register (PCDDR) Port C data register (PCDR) Port C register (PORTC) Port C pull-up MOS control register (PCPCR) Port C open drain control register (PCODR) 10.11.1 Port C Data Direction Register (PCDDR) The individual bits of PCDDR specify input or output for the pins of port C.
PAGE 666
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.11.2 Port C Data Register (PCDR) PCDR stores output data for the port C pins. Bit Bit Name Initial Value R/W Description 7 PC7DR 0 R/W 6 PC6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PC5DR 0 R/W 4 PC4DR 0 R/W 3 PC3DR 0 R/W 2 PC2DR 0 R/W 1 PC1DR 0 R/W 0 PC0DR 0 R/W 10.11.3 Port C Register (PORTC) PORTC shows the pin states of port C.
PAGE 667
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.11.4 Port C Pull-Up MOS Control Register (PCPCR) PCPCR controls on/off of the input pull-up MOS for port C. PCPCR is valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 PC7PCR 0 R/W 6 PC6PCR 0 R/W When in a input port state, setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 668
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.11.6 Pin Functions Port C pins also function as the pins for TPU I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. • PC7/A7/TIOCB11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOB3 to IOB0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC7DDR.
PAGE 669
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC6/A6/TIOCA11 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 11 settings (by bits MD3 to MD0 in TMDR_11, bits IOA3 to IOA0 in TIOR_11, and bits CCLR1 and CCLR0 in TCR_11), and bit PC6DDR.
PAGE 670
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC5/A5/TIOCB10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOB3 to IOB0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC5DDR.
PAGE 671
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC4/A4/TIOCA10 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 10 settings (by bits MD3 to MD0 in TMDR_10, bits IOA3 to IOA0 in TIOR_10, and bits CCLR1 and CCLR0 in TCR_10), and bit PC4DDR.
PAGE 672
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC3/A3/TIOCD9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOD3 to IOD0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC3DDR.
PAGE 673
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC2/A2/TIOCC9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOC3 to IOC0 in TIORL_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC2DDR.
PAGE 674
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC1/A1/TIOCB9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOB3 to IOB0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC1DDR.
PAGE 675
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PC0/A0/TIOCA9 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, TPU channel 9 settings (by bits MD3 to MD0 in TMDR_9, bits IOA3 to IOA0 in TIORH_9, and bits CCLR2 to CCLR0 in TCR_9), and bit PC0DDR.
PAGE 676
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.11.7 Port C Input Pull-Up MOS States Port C has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3, 4, and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis In modes 3, 4, and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.
PAGE 677
H8S/2426, H8S/2426R, H8S/2424 Group 10.12 Section 10 I/O Ports Port D Port D is an 8-bit I/O port that also has other functions. Port D has the following registers. • • • • • Port D data direction register (PDDDR) Port D data register (PDDR) Port D register (PORTD) Port D pull-up MOS control register (PDPCR) Port D open drain control register (PDODR) 10.12.1 Port D Data Direction Register (PDDDR) The individual bits of PDDDR specify input or output for the pins of port D.
PAGE 678
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.12.2 Port D Data Register (PDDR) PDDR stores output data for the port D pins. Bit Bit Name Initial Value R/W Description 7 PD7DR 0 R/W 6 PD6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PD5DR 0 R/W 4 PD4DR 0 R/W 3 PD3DR 0 R/W 2 PD2DR 0 R/W 1 PD1DR 0 R/W 0 PD0DR 0 R/W 10.12.3 Port D Register (PORTD) PORTD shows the pin states of port D.
PAGE 679
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.12.4 Port D Pull-Up MOS Control Register (PDPCR) PDPCR controls on/off of the input pull-up MOS for port D. PDPCR is valid in mode 7. Bit Bit Name Initial Value R/W Description 7 PD7PCR 0 R/W 6 PD6PCR 0 R/W When PDDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin. 5 PD5PCR 0 R/W 4 PD4PCR 0 R/W 3 PD3PCR 0 R/W 2 PD2PCR 0 R/W 1 PD1PCR 0 R/W 0 PD0PCR 0 R/W 10.12.
PAGE 680
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.12.6 Pin Functions Port D pins also function as the pins for data I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below.
PAGE 681
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.12.7 Port D Input Pull-Up MOS States Port D has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in modes 3 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In modes 3 and 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.6 summarizes the input pull-up MOS states.
PAGE 682
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.13 Port E Port E is an 8-bit I/O port that also has other functions. Port E has the following registers. • • • • • Port E data direction register (PEDDR) Port E data register (PEDR) Port E register (PORTE) Port E pull-up MOS control register (PEPCR) Port E open drain control register (PEODR) 10.13.1 Port E Data Direction Register (PEDDR) The individual bits of PEDDR specify input or output for the pins of port E.
PAGE 683
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.13.2 Port E Data Register (PEDR) PEDR stores output data for the port E pins. Bit Bit Name Initial Value R/W Description 7 PE7DR 0 R/W 6 PE6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W 10.13.3 Port E Register (PORTE) PORTE shows the pin states of port E.
PAGE 684
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.13.4 Port E Pull-Up MOS Control Register (PEPCR) PEPCR controls on/off of the input pull-up MOS for port E. PEPCR is valid in 8-bit bus mode. Bit Bit Name Initial Value R/W Description 7 PE7PCR 0 R/W 6 PE6PCR 0 R/W When PEDDR = 0 (input port), setting the corresponding bit to 1 turns on the input pull-up MOS for that pin.
PAGE 685
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.13.6 Pin Functions Port E pins also function as the pins for data I/Os and address outputs. The correspondence between the register specification and the pin functions is shown below. • PE7/D7/AD7, PE6/D6/AD6, PE5/D5/AD5, PE4/D4/AD4, PE3/D3/AD3, PE2/D2/AD2, PE1/D1/AD1, PE0/D0/AD0 The pin function is switched as shown below according to the combination of the operating mode, bus mode, bit EXPE, and bit PEnDDR of the bus controller.
PAGE 686
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.13.7 Port E Input Pull-Up MOS States Port E has a built-in input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be used in 8-bit bus mode or in modes 3 and 7. The input pull-up MOS can be specified as on or off on a bit-by-bit basis. In 8-bit bus mode or in modes 3 and 7, when a PEDDR bit is cleared to 0, setting the corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin. Table 10.
PAGE 687
H8S/2426, H8S/2426R, H8S/2424 Group 10.14 Section 10 I/O Ports Port F Port F is an 8-bit I/O port that also has other functions. Port F has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.
PAGE 688
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.14.1 Port F Data Direction Register (PFDDR) The individual bits of PFDDR specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PAGE 689
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 7 PF7DDR 1/0* W • 6 PF6DDR 0 W 5 PF5DDR 0 W 4 PF4DDR 0 W 3 PF3DDR 0 W 2 PF2DDR 0 W 1 PF1DDR 0 W 0 PF0DDR 0 W Modes 3 and 7 (EXPE = 0) Pin PF7 functions as the φ output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. Pins PF6 to PF0 are I/O ports, and their functions can be switched with PFDDR. Notes: 1.
PAGE 690
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.14.2 Port F Data Register (PFDR) PFDR stores output data for the port F pins. Bit Bit Name Initial Value R/W Description 7 PF7DR 0 R/W 6 PF6DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W 10.14.3 Port F Register (PORTF) PORTF shows the pin states of port F.
PAGE 691
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.14.4 Port F Open Drain Control Register (PFODR) PFODR specifies the output type of each port F pin.
PAGE 692
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PF6/AS/AH The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit MPXE in MPXCR of the bus controller, bit ASOE in PFCR2, and bit PF6DDR.
PAGE 693
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PF3/LWR/SSO0-C The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bit LWROE in PFCR2, bits SSOS1 and SSOS0 in PFCR5, and bit PF3DDR.
PAGE 694
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PF2/LCAS*7/DQML*6/IRQ15-A/SSI0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR*7 of the bus controller, bits ABW5 to ABW2 in ABWCR, bits SSI0S1 and SSI0S0 in PFCR5, and bit PF2DDR.
PAGE 695
H8S/2426, H8S/2426R, H8S/2424 Group SSU (1) (1) (3) (3) Section 10 I/O Ports (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2) settings SSUMS 0 0 BIDE 0 1* MSS 0 TE 1 0 1 0 1 1* 2 0 0 1 0 1 1 0 0 1 0 1 1 0 1 RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 Pin state ⎯ ⎯ SSI SSI SSI ⎯ SSI ⎯ ⎯ ⎯ ⎯ SSI ⎯ SSI SSI ⎯ SSI output output input input input input input input [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port).
PAGE 696
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) Areas 2 to 5 ⎯ CS6E ⎯ SSU settings (1) in table below PF2DDR 0 Pin function (2) in table below 1 PF2 input (3) in table below ⎯ 3 0* 1 PF2 output 4 SSI0-C output*2*4 SSI0-C input* * Notes: 1. When using as SSI0-C input, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other register setting. 2. When using as SSI0-C output, set SSI0S1 and SSI0S0 in PFCR5 to B'10 before other register setting. 3.
PAGE 697
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PF1/UCAS*7/DQMU*6/IRQ14-A/SSCK0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits RMTS2 to RMTS0 in DRAMCR*7 of the bus controller, bits SSCK0S1 and SSCK0S0 in PFCR5, and bit PF1DDR.
PAGE 698
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports SSU settings (1) (2) SSUMS (1) (3) (1) (2) 0 MSS (1) (3) 1 0 1 0 1 SCKS 0 1 0 1 0 1 0 1 Pin state ⎯ SSCK input ⎯ SSCK output ⎯ SSCK input ⎯ SSCK output [Legend] ⎯: Not used as the SSU pin (can be used as an I/O port). Note: See tables 19.4 to 19.6.
PAGE 699
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) Areas 2 to 5 ⎯ CS5E ⎯ SSU settings (1) in table below PF1DDR 0 Pin function (2) in table below 1 PF1 input (3) in table below ⎯ 3 0* PF1 output 1 4 SSCK0-C input* * SSCK0-C output*2 Notes: 1. When using as SSCK0-C input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before other register setting. 2. When using as SSCK0-C output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before other register setting. 3.
PAGE 700
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PF0/WAIT-A/ADTRG0-B/SCS0-C (H8S/2426 Group and H8S/2426R Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
PAGE 701
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) ⎯ WAITE SSU settings (1) in table below (4) in table below (3) in table below 0 1 0*5 0*5 ⎯ PF0 input PF0 output SCS0-C 2 6 input* * SCS0-C I/O*4*6 SCS0-C output*3*6 PF0DDR Pin function (2) in table below ADTRG0-B input* 1 Notes: 1. ADTRG0-B input when the ADTRG0S bit in PFCR4 is 1, TRGS1 = TRGS0 = 0, and EXTRGS = 1 2.
PAGE 702
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A*8 (H8S/2424 Group) The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR*8, bits MSS, CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and EXTRGS in ADCR_0 of the ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4, bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
PAGE 703
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Modes 3 and 7 (EXPE = 0) OEE ⎯ Area 2 ⎯ WAITE ⎯ SSU settings (1) in table below PF0DDR 0 PF0 input Pin function (2) in table below (4) in table below (3) in table below 1 0*6 0*6 ⎯ PF0 output SCS0-C input*3*7 SCS0-C I/O*5*7 SCS0-C output*4*7 ADTRG0-B input* 2 Notes: 1. OE-A input when the OES bit in PFCR2 is 1. 2. ADTRG0-B input when TRGS1 = TRGS0 = 0, EXTRGS = 1 or TRGS1 = TRGS0 = EXTRGS = 1. 3.
PAGE 704
Section 10 I/O Ports 10.15 H8S/2426, H8S/2426R, H8S/2424 Group Port G Port G is a 7-bit I/O port that also has other functions. Port G has the following registers. • • • • • • Port G data direction register (PGDDR) Port G data register (PGDR) Port G register (PORTG) Port function control register 0 (PFCR0) Port function control register 4 (PFCR4) Port G open drain control register (PGODR) Page 674 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 705
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.15.1 Port G Data Direction Register (PGDDR) The individual bits of PGDDR specify input or output for the pins of port G. PGDDR cannot be read; if it is, an undefined value will be read.
PAGE 706
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.15.2 Port G Data Register (PGDR) PGDR stores output data for the port G pins. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved This bit is always read as 0, and cannot be modified. 6 PG6DR 0 R/W 5 PG5DR 0 R/W 4 PG4DR 0 R/W 3 PG3DR 0 R/W 2 PG2DR 0 R/W 1 PG1DR 0 R/W 0 PG0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.15.
PAGE 707
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.15.4 Port G Open Drain Control Register (PGODR) PGODR specifies the output type of each port G pin. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ Reserved This bit is always read as 0. Only the initial value should be written to this bit.
PAGE 708
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.15.5 Pin Functions Port G pins also function as the pins for bus control signal I/Os. The correspondence between the register specification and the pin functions is shown below. • PG6/BREQ-A The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit BRLE in BCR of the bus controller, bit BREQS in PFCR4, and bit PG6DDR.
PAGE 709
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PG4/BREQO-A/CS4* The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits BRLE and BREQOE, in BCR of the bus controller, bit BREQOS in PFCR4, bit SC4E in PFCR0, and bit PG4DDR.
PAGE 710
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PG3/CS3/RAS3*2/CAS*1 The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS3E in PFCR0, and bit PG3DDR.
PAGE 711
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PG2/CS2/RAS2*2/RAS*1 The pin function is switched as shown below according to the combination of the operating mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit PG2DDR.
PAGE 712
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.16 Port H Note: Port H is not supported in the H8S/2424 Group. Port H is a 4-bit I/O port that also has other functions. Port H has the following registers. For the port function control registers, refer to section 10.18, Port Function Control Registers.
PAGE 713
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W 0 PH0DDR 0 W Description Pin PH1 functions as the SDRAMφ*1 output pin when the SDPSTP bit is 0 in the H8S/2426R Group. In the H8S/2426 Group or when the SDPSTP bit is 1 in the H8S/2426R Group, if bit CS5E is set to 1 while area 5 is specified as normal space, pin PH1 functions as the CS5 output pin when bit PH1DDR is set to 1, and functions as an I/O port when the bit is cleared to 0.
PAGE 714
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.16.2 Port H Data Register (PHDR) PHDR stores output data for the port H pins. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 3 PH3DR 0 R/W 2 PH2DR 0 R/W 1 PH1DR 0 R/W 0 PH0DR 0 R/W Output data for a pin is stored when the pin function is specified as a general purpose I/O. 10.16.3 Port H Register (PORTH) PORTH shows the pin states of port H.
PAGE 715
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.16.4 Port H Open Drain Control Register (PHODR) PHODR specifies the output type of each port H pin. Bit Bit Name 7 to 4 ⎯ Initial Value R/W Description All 0 ⎯ Reserved These bits are always read as 0. Only the initial values should be written to these bits.
PAGE 716
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.16.5 Pin Functions Port H pins also function as bus control signal I/Os and interrupt inputs. The correspondence between the register specification and the pin functions is shown below. • PH3/CS7/OE-A*3/CKE-A*2/IRQ7-B The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bit OEE in DRAMCR of the bus controller, bit OES in PFCR2, bit CS7E in PFCR0, and bit PH3DDR.
PAGE 717
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • Mode 7 (EXPE = 0) OEE ⎯ OES ⎯ RMTS2 to RMTS0 ⎯ CS7E ⎯ PH3DDR 0 Pin function 1 PH3 input PH3 output IRQ7-B input*1 Notes: 1. IRQ7-B input when the ITS7 bit in ITSR is 1. 2. Not supported in the H8S/2426 Group. 3. Not supported in the 5-V version. • PH2/CS6/IRQ6-B The pin function is switched as shown below according to the combination of the operating mode, bit CS6E in PFCR0, and bit PH2DDR.
PAGE 718
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PH1/CS5/RAS5*2/SDRAMφ*1 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR.
PAGE 719
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports • PH0/CS4/RAS4*2/WE*1 The pin function is switched as shown below according to the combination of the operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS4E in PFCR0, and bit PH0DDR.
PAGE 720
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.17 Port J Note: Port J is not supported in the H8S/2424 Group and in the 145-pin package. Port J is a 3-bit I/O port. Port J has the following registers. • • • • Port J data direction register (PJDDR) Port J data register (PJDR) Port J register (PORT3) Port J open drain control register (PJODR) 10.17.1 Port J Data Direction Register (PJDDR) The individual bits of PJDDR specify input or output for the pins of port J.
PAGE 721
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.17.3 Port J Register (PORTJ) PORTJ shows the pin states of port J. PORTJ cannot be modified. Bit Bit Name Initial Value R/W Description 7 to 3 ⎯ Undefined ⎯ Reserved If these bits are read, they will return an undefined value. 2 PJ2 ⎯* R The pin state is always read from this register. 1 PJ1 ⎯* R 0 PJ0 ⎯* R If this register is read, the PJDR values are read for the bits with the corresponding PJDDR bits set to 1.
PAGE 722
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.17.5 Pin Functions Port J pins function only as I/O ports. The correspondence between the register specification and the pin functions is shown below. • PJ2 The PJ2 pin is an input-only pin. Pin function PJ2 input • PJ1, PJ0 The pin function is switched as shown below according to bit PJnDDR. PJnDDR Pin function 0 1 PJn input PJn output [Legend] n = 1 or 0 Page 692 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 723
H8S/2426, H8S/2426R, H8S/2424 Group 10.18 Section 10 I/O Ports Port Function Control Registers The port function controller performs I/O port control. The setting of input or output for each pin should be enabled only after the input or output destination has been selected. The port function controller has the following registers.
PAGE 724
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.18.2 Port Function Control Register 1 (PFCR1) PFCR1 enables or disables address output (A23 to A16). Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7. Bit Bit Name Initial Value R/W Description 7 A23E 1 R/W Address 23 Enable Enables or disables output for address output 23 (A23).
PAGE 725
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 1 A17E 1 R/W Address 17 Enable Enables or disables output for address output 17 (A17). 0: DR output when PA1DDR = 1 1: A17 output when PA1DDR = 1 0 A16E 1 R/W Address 16 Enable Enables or disables output for address output 16 (A16). 0: DR output when PA0DDR = 1 1: A16 output when PA0DDR = 1 R01UH0310EJ0500 Rev. 5.
PAGE 726
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.18.3 Port Function Control Register 2 (PFCR2) PFCR2 enables or disables AS output, LWR output, and OE output. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 3 ASOE 1 R/W AS Output Enable Enables or disables the AS output pin.
PAGE 727
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.18.4 Port Function Control Register 3 (PFCR3) PFCR3 switches the functions of the PPG output pin, TPU input/output pin, and TMR input/output pin. Bit Bit Name Initial Value R/W Description 7 ⎯ 1 ⎯ Reserved This bit is always read as 1. Only the initial value should be written to this bit. 6 PPGS 0 R/W PPG Pin Select Selects the output pins of PO5 to PO0.
PAGE 728
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 4 TMRS 0 R/W TMR Pin Select Selects the output pins of TMO1 and TMO0 and input pins of TMCI1, TMCI0, TMRI1, and TMRI0.
PAGE 729
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports Bit Bit Name Initial Value R/W Description 5 BACKS 0 R/W BACK Pin Select Selects the BACK output pin. 0: PG5/BACK-A is selected 1: P52/BACK-B is selected 4 BREQOS 0 R/W BREQO Pin Select Selects the BREQO output pin. 0: PG4/BREQO-A is selected 1: P50/BREQO-B is selected 3 ⎯ 0 ⎯ Reserved This bit is always read as 0. Only the initial value should be written to this bit. 2 TXD4S 0 R/W TxD4 Pin Select Selects the TxD4 output pin.
PAGE 730
H8S/2426, H8S/2426R, H8S/2424 Group Section 10 I/O Ports 10.18.6 Port Function Control Register 5 (PFCR5) PFCR5 switches the functions of the SSU input/output pins. Bit Bit Name Initial Value R/W Description 7 SSO0S1 0 R/W SSO0 Pin Select 6 SSO0S0 0 R/W Selects the SSO0 input/output pin. 00: P14/SSO0-A is selected 01: PA7/SSO0-B is selected 10: PF3/SSO0-C is selected 11: Setting prohibited 5 SSI0S1 0 R/W SSI0 Pin Select 4 SSI0S0 0 R/W Selects the SSI0 input/output pin.
PAGE 731
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Section 11 16-Bit Timer Pulse Unit (TPU) This LSI has two on-chip 16-bit timer pulse units (TPU: unit 0 and unit 1) which each comprises six 16-bit timer channels, resulting in a total of 12 channels. The functions of unit 0 are listed in table 11.1, and the functions of unit 1 are listed in table 11.2. The block diagram of unit 0 is shown in figure 11.1 and the block diagram of unit 1 is shown in figure 11.2.
PAGE 732
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 733
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC activation TGRA_0 compare match or input capture TGRA_1 compare match or input capture TGRA_2 compare match or input capt
PAGE 734
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 735
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Item Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 DTC activation TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture DMAC activation ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ A/D converter trigger TGRA_6 compare match or input capture TGRA_7 compare match or input
PAGE 736
H8S/2426, H8S/2426R, H8S/2424 Group TGRD TGRB TGRC TGRB Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U Internal data bus A/D conversion start request signal TGRD TGRB TGRB TGRB PPG output trigger signal TGRC TCNT TCNT TGRA TCNT TGRA Bus interface TGRB TCNT TCNT TGRA TCNT TGRA Module data bus TGRA TSR TSR TIER TSR TIER TIOR TIORH TIORL TIER: TSR: TGR (A, B, C, D): TCNT: TGRA TSR TIER TSR TS
PAGE 737
H8S/2426, H8S/2426R, H8S/2424 Group TIER: TSR: TGR (A, B, C, D): TCNT: TGRD TGRB TGRC TGRB Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U Internal data bus TGRD TGRB TGRB TGRB A/D conversion start request signal TGRC TCNT TCNT TGRA TCNT TGRA TGRA Bus interface TGRB TCNT TCNT TGRA TCNT Module data bus TGRA TGRA TSR TIER TSR TIER TSR TIER TSTR TSYR TSR TIER TSR TIER TIOR TIORH TIORL
PAGE 738
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.2 Input/Output Pins Table 11.
PAGE 739
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol I/O Function 0 4 TIOCA4 I/O TGRA_4 input capture input/output compare output/ PWM output pin TIOCB4 I/O TGRB_4 input capture input/output compare output/ PWM output pin TIOCA5 I/O TGRA_5 input capture input/output compare output/ PWM output pin TIOCB5 I/O TGRB_5 input capture input/output compare output/ PWM output pin TCLKE Input External clock E input pin (Channel 7 and 11 phase counting
PAGE 740
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Symbol I/O Function 1* 9 TIOCA9 I/O TGRA_9 input capture input/output compare output/ PWM output pin TIOCB9 I/O TGRB_9 input capture input/output compare output/ PWM output pin TIOCC9 I/O TGRC_9 input capture input/output compare output/ PWM output pin TIOCD9 I/O TGRD_9 input capture input/output compare output/ PWM output pin TIOCA10 I/O TGRA_10 input capture input/output compare output/PWM outp
PAGE 741
H8S/2426, H8S/2426R, H8S/2424 Group 11.3 Section 11 16-Bit Timer Pulse Unit (TPU) Register Descriptions The TPU has the following registers in each channel. The descriptions in this section refer to the registers of unit 0.
PAGE 742
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2426, H8S/2426R, H8S/2424 Group Channel 2 • Timer control register_2 (TCR_2) • Timer mode register_2 (TMDR_2) • Timer I/O control register_2 (TIOR_2) • Timer interrupt enable register_2 (TIER_2) • Timer status register_2 (TSR_2) • Timer counter_2 (TCNT_2) • Timer general register A_2 (TGRA_2) • Timer general register B_2 (TGRB_2) Channel 3 • Timer control register_3 (TCR_3) • Timer mode register_3 (TMDR_3) • Timer I/O control register H_3 (TIORH_3) • Timer I/O
PAGE 743
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Channel 5 • Timer control register_5 (TCR_5) • Timer mode register_5 (TMDR_5) • Timer I/O control register_5 (TIOR_5) • Timer interrupt enable register_5 (TIER_5) • Timer status register_5 (TSR_5) • Timer counter_5 (TCNT_5) • Timer general register A_5 (TGRA_5) • Timer general register B_5 (TGRB_5) Common Registers of Unit 0 • Timer start register (TSTR) • Timer synchronous register (TSYR) Unit 1: Channel 6 • Timer control regist
PAGE 744
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2426, H8S/2426R, H8S/2424 Group Channel 7 • Timer control register_7 (TCR_7) • Timer mode register_7 (TMDR_7) • Timer I/O control register_7 (TIOR_7) • Timer interrupt enable register_7 (TIER_7) • Timer status register_7 (TSR_7) • Timer counter_7 (TCNT_7) • Timer general register A_7 (TGRA_7) • Timer general register B_7 (TGRB_7) Channel 8 • Timer control register_8 (TCR_8) • Timer mode register_8 (TMDR_8) • Timer I/O control register_8 (TIOR_8) • Timer interru
PAGE 745
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Channel 10 • Timer control register_10 (TCR_10) • Timer mode register_10 (TMDR_10) • Timer I/O control register_10 (TIOR_10) • Timer interrupt enable register_10 (TIER_10) • Timer status register_10 (TSR_10) • Timer counter_10 (TCNT_10) • Timer general register A_10 (TGRA_10) • Timer general register B_10 (TGRB_10) Channel 11 • Timer control register_11 (TCR_11) • Timer mode register_11 (TMDR_11) • Timer I/O control register_11 (
PAGE 746
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.1 Timer Control Register (TCR) The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 CCLR2 0 R/W Counter Clear 2 to 0 6 CCLR1 0 R/W 5 CCLR0 0 R/W These bits select the TCNT counter clearing source. See tables 11.
PAGE 747
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 748
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 749
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 750
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 751
H8S/2426, H8S/2426R, H8S/2424 Group 11.3.2 Section 11 16-Bit Timer Pulse Unit (TPU) Timer Mode Register (TMDR) TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only when TCNT operation is stopped. Bit Bit Name Initial Value R/W Description 7 ⎯ 1 ⎯ Reserved 6 ⎯ 1 ⎯ These bits are always read as 1 and cannot be modified.
PAGE 752
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.12 MD3 to MD0 Bit 3 1 MD3* Bit 2 MD2*2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 1 1 0 1 1 x x 0 Phase counting mode 3 1 Phase counting mode 4 x ⎯ [Legend] x: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2.
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H8S/2426, H8S/2426R, H8S/2424 Group 11.3.3 Section 11 16-Bit Timer Pulse Unit (TPU) Timer I/O Control Register (TIOR) TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0).
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H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 755
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 756
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 757
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 758
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 759
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 760
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 761
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 763
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 764
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 765
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 767
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 768
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 769
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 770
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.4 Timer Interrupt Enable Register (TIER) TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TTGE 0 R/W A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match.
PAGE 771
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Bit Bit Name Initial value R/W Description 2 TGIEC 0 R/W TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified.
PAGE 772
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.5 Timer Status Register (TSR) TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each channel. Bit Bit Name Initial value R/W Description 7 TCFD 1 R Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
PAGE 773
H8S/2426, H8S/2426R, H8S/2424 Group Bit 3 Bit Name TGFD Initial value 0 Section 11 16-Bit Timer Pulse Unit (TPU) R/W Description 1 R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
PAGE 774
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Bit 1 Bit Name TGFB Initial value 0 R/W Description 1 R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match.
PAGE 775
H8S/2426, H8S/2426R, H8S/2424 Group 11.3.6 Section 11 16-Bit Timer Pulse Unit (TPU) Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 11.3.
PAGE 776
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.9 Timer Synchronous Register (TSYR) TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Bit Bit Name Initial value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0.
PAGE 777
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.10 Timer Start Register B (TSTRB) TSTRB selects operation/stoppage for channels 6 to 11. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit Bit Name Initial value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0. 5 CST11 0 R/W Counter Start 11 to 6 4 CST10 0 R/W These bits select operation or stoppage for TCNT.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.3.11 Timer Synchronous Register B (TSYRB) TSYRB selects independent operation or synchronous operation for the TCNT counters of channels 6 to 11. A channel performs synchronous operation when the corresponding bit in TSYRB is set to 1. Bit Bit Name Initial value R/W Description 7 ⎯ 0 ⎯ Reserved 6 ⎯ 0 ⎯ The write value should always be 0.
PAGE 779
H8S/2426, H8S/2426R, H8S/2424 Group 11.4 Operation 11.4.1 Basic Functions Section 11 16-Bit Timer Pulse Unit (TPU) Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting.
PAGE 780
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
PAGE 781
H8S/2426, H8S/2426R, H8S/2424 Group (b) Section 11 16-Bit Timer Pulse Unit (TPU) Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.
PAGE 782
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2426, H8S/2426R, H8S/2424 Group Figure 11.5 illustrates periodic counter operation. TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 11.5 Periodic Counter Operation Page 752 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 783
H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) Waveform Output by Compare Match The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of setting procedure for waveform output by compare match Figure 11.6 shows an example of the setting procedure for waveform output by a compare match.
PAGE 784
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (b) Examples of waveform output operation Figure 11.7 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
PAGE 785
H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 11 16-Bit Timer Pulse Unit (TPU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, 4, 6, 7, 9, and 10 it is also possible to specify another channel's counter input clock or compare match signal as the input capture source.
PAGE 786
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (b) Example of input capture operation Figure 11.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
PAGE 787
H8S/2426, H8S/2426R, H8S/2424 Group (1) Section 11 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Setting Procedure Figure 11.11 shows an example of the synchronous operation setting procedure.
PAGE 788
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) Example of Synchronous Operation Figure 11.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2.
PAGE 789
H8S/2426, H8S/2426R, H8S/2424 Group 11.4.3 Section 11 16-Bit Timer Pulse Unit (TPU) Buffer Operation Buffer operation, provided for channels 0, 3, 6, and 9, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 11.29 shows the register combinations used in buffer operation. Table 11.
PAGE 790
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 11.14. Input capture signal Timer general register Buffer register TCNT Figure 11.14 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure Figure 11.
PAGE 791
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of Buffer Operation (a) When TGR is an output compare register Figure 11.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
PAGE 792
Section 11 16-Bit Timer Pulse Unit (TPU) (b) H8S/2426, H8S/2426R, H8S/2424 Group When TGR is an input capture register Figure 11.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
PAGE 793
H8S/2426, H8S/2426R, H8S/2424 Group 11.4.4 Section 11 16-Bit Timer Pulse Unit (TPU) Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4, channel 7, or channel 10) counter clock at overflow/underflow of TCNT_2 (TCNT_5, TCNT_8, or TCNT_11) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 11.
PAGE 794
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of Cascaded Operation Figure 11.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
PAGE 795
H8S/2426, H8S/2426R, H8S/2424 Group 11.4.5 Section 11 16-Bit Timer Pulse Unit (TPU) PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register.
PAGE 796
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 797
H8S/2426, H8S/2426R, H8S/2424 Group (1) Section 11 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure Figure 11.21 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
PAGE 798
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) Examples of PWM Mode Operation Figure 11.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as the duty cycle.
PAGE 799
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform.
PAGE 800
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Figure 11.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
PAGE 801
H8S/2426, H8S/2426R, H8S/2424 Group 11.4.6 Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, 5, 7, 8, 10, and 11.
PAGE 802
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (1) Example of Phase Counting Mode Setting Procedure Figure 11.25 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 11.
PAGE 803
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Table 11.
PAGE 804
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) b. Phase counting mode 2 Figure 11.27 shows an example of phase counting mode 2 operation, and table 11.34 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 11.27 Example of Phase Counting Mode 2 Operation Table 11.
PAGE 805
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) c. Phase counting mode 3 Figure 11.28 shows an example of phase counting mode 3 operation, and table 11.35 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.28 Example of Phase Counting Mode 3 Operation Table 11.
PAGE 806
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) d. Phase counting mode 4 Figure 11.29 shows an example of phase counting mode 4 operation, and table 11.36 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 11.29 Example of Phase Counting Mode 4 Operation Table 11.
PAGE 807
H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 11 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example Figure 11.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
PAGE 808
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture) TCNT_0 TGRA_0 (speed control cycle) + - TGRC_0 (position control cycle) + - TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 11.30 Phase Counting Mode Application Example Page 778 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 809
H8S/2426, H8S/2426R, H8S/2424 Group 11.5 Section 11 16-Bit Timer Pulse Unit (TPU) Interrupt Sources There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.
PAGE 810
Section 11 16-Bit Timer Pulse Unit (TPU) H8S/2426, H8S/2426R, H8S/2424 Group Table 11.
PAGE 811
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) Unit Channel Name Interrupt Source Interrupt Flag DTC Activation DMAC Activation 1 TGI6A TGRA_6 input capture/compare match TGFA_6 Possible Not possible TGI6B TGRB_6 input capture/compare match TGFB_6 Possible Not possible TGI6C TGRC_6 input capture/compare match TGFC_6 Possible Not possible TGI6D TGRD_6 input capture/compare match TGFD_6 Possible Not possible 6 7 8 9 10 11 Note: TCI6V TCNT_6 ov
PAGE 812
Section 11 16-Bit Timer Pulse Unit (TPU) (1) H8S/2426, H8S/2426R, H8S/2424 Group Input Capture/Compare Match Interrupt An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0.
PAGE 813
H8S/2426, H8S/2426R, H8S/2424 Group 11.6 Section 11 16-Bit Timer Pulse Unit (TPU) DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 9, Data Transfer Controller (DTC). A total of 32 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0, 3, 6, and 9, and two each for channels 1, 2, 4, 5, 7, 8, 10, and 11. 11.
PAGE 814
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.9 Operation Timing 11.9.1 Input/Output Timing (1) TCNT Count Timing Figure 11.31 shows TCNT count timing in internal clock operation, and figure 11.32 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock N–1 TCNT N N+1 N+2 Figure 11.
PAGE 815
H8S/2426, H8S/2426R, H8S/2424 Group (2) Section 11 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the (TIOC pin) TCNT input clock is generated.
PAGE 816
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (3) Input Capture Signal Timing Figure 11.34 shows input capture signal timing. φ Input capture input Input capture signal TCNT TGR N N+1 N+2 N N+2 Figure 11.34 Input Capture Input Signal Timing Page 786 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 817
H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 11 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 11.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 11.36 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 11.
PAGE 818
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (5) Buffer Operation Timing Figures 11.37 and 11.38 show the timings in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 11.37 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 11.38 Buffer Operation Timing (Input Capture) Page 788 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 819
H8S/2426, H8S/2426R, H8S/2424 Group 11.9.2 (1) Section 11 16-Bit Timer Pulse Unit (TPU) Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match Figure 11.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 11.39 TGI Interrupt Timing (Compare Match) R01UH0310EJ0500 Rev. 5.
PAGE 820
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (2) TGF Flag Setting Timing in Case of Input Capture Figure 11.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing. φ Input capture signal TCNT TGR N N TGF flag TGI interrupt Figure 11.40 TGI Interrupt Timing (Input Capture) Page 790 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 821
H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 11 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing Figure 11.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 11.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 11.
PAGE 822
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) (4) Status Flag Clearing Timing After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 11.43 shows the timing for status flag clearing by the CPU, and figure 11.44 shows the timing for status flag clearing by the DTC or DMAC.
PAGE 823
H8S/2426, H8S/2426R, H8S/2424 Group 11.10 Section 11 16-Bit Timer Pulse Unit (TPU) Usage Notes 11.10.1 Module Stop Function Setting TPU operation can be disabled or enabled using the module stop control register. The initial setting is for TPU operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 23, Power-Down Modes. 11.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.
PAGE 824
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: φ f= (N + 1) Where f: Counter frequency φ: Operating frequency N: TGR set value 11.10.
PAGE 825
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 11.47 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 11.47 Contention between TCNT Write and Increment Operations R01UH0310EJ0500 Rev. 5.
PAGE 826
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 11.48 shows the timing in this case.
PAGE 827
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 11.49 shows the timing in this case. TGR write cycle T2 T1 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 11.
PAGE 828
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.8 Contention between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 11.50 shows the timing in this case. TGR read cycle T1 T2 φ TGR address Address Read signal Input capture signal TGR X Internal data bus M M Figure 11.
PAGE 829
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.9 Contention between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 11.51 shows the timing in this case. TGR write cycle T2 T1 φ Address TGR address Write signal Input capture signal TCNT M M TGR Figure 11.
PAGE 830
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.10 Contention between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 11.52 shows the timing in this case.
PAGE 831
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.11 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clearing signal TGF Disabled TCFV Figure 11.
PAGE 832
H8S/2426, H8S/2426R, H8S/2424 Group Section 11 16-Bit Timer Pulse Unit (TPU) 11.10.12 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, when overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 11.54 shows the operation timing when there is contention between TCNT write and overflow.
PAGE 833
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) Section 12 Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that can operate both simultaneously and independently. The block diagram of PPG is shown in figure 12.1. 12.
PAGE 834
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) Compare match signals Control logic PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 [Legend] PMR: PCR: NDERH: NDERL: NDRH: NDRL: PODRH: PODRL: NDERH NDERL PMR PCR Pulse output pins, group 3 PODRH NDRH (NDRHH, NDRHL) PODRL NDRL (NDRLH, NDRLL) Pulse output pins, group 2 Internal data bus Pulse output pins, group 1 Pulse output pins, group 0 PPG output mode register PPG output control regist
PAGE 835
H8S/2426, H8S/2426R, H8S/2424 Group 12.2 Section 12 Programmable Pulse Generator (PPG) Input/Output Pins Table 12.1 shows the PPG pin configuration. Table 12.1 Pin Configuration Pin Name I/O Function PO15 Output Group 3 pulse output PO14 Output PO13 Output PO12 Output PO11 Output PO10 Output PO9 Output PO8 Output PO7 Output PO6 Output PO5 Output PO4 Output PO3 Output PO2 Output PO1 Output PO0 Output R01UH0310EJ0500 Rev. 5.
PAGE 836
Section 12 Programmable Pulse Generator (PPG) 12.3 H8S/2426, H8S/2426R, H8S/2424 Group Register Descriptions The PPG has the following registers. • • • • • • • • Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR) Page 806 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 837
H8S/2426, H8S/2426R, H8S/2424 Group 12.3.1 Section 12 Programmable Pulse Generator (PPG) Next Data Enable Registers H, L (NDERH, NDERL) NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the PPG, set the corresponding DDR to 1.
PAGE 838
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 12.3.2 Output Data Registers H, L (PODRH, PODRL) PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified.
PAGE 839
H8S/2426, H8S/2426R, H8S/2424 Group 12.3.3 Section 12 Programmable Pulse Generator (PPG) Next Data Registers H, L (NDRH, NDRL) NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. • NDRH (NDRHH, NDRHL)* If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
PAGE 840
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) • NDRHH* Bit Bit Name Initial Value R/W Description 7 NDR15 0 R/W Next Data Register 15 to 12 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W The register contents are transferred to the corresponding PODRH bits by the output trigger specified with PCR. 3 to 0 ⎯ All 1 ⎯ Reserved 1 is always read and write is disabled.
PAGE 841
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) • NDRLH* Bit Bit Name Initial Value R/W Description 7 NDR7 0 R/W Next Data Register 7 to 4 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. 3 to 0 ⎯ All 1 ⎯ Reserved 1 is always read and write is disabled.
PAGE 842
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 12.3.4 PPG Output Control Register (PCR) PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 12.3.5, PPG Output Mode Register (PMR). Bit Bit Name Initial Value R/W Description 7 G3CMS1 1 R/W Group 3 Compare Match Select 1 and 0 6 G3CMS0 1 R/W Select output trigger of pulse output group 3.
PAGE 843
H8S/2426, H8S/2426R, H8S/2424 Group 12.3.5 Section 12 Programmable Pulse Generator (PPG) PPG Output Mode Register (PMR) PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 12.4.
PAGE 844
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) Bit Bit Name Initial Value R/W Description 3 G3NOV 0 R/W Group 3 Non-Overlap Selects normal or non-overlapping operation for pulse output group 3.
PAGE 845
H8S/2426, H8S/2426R, H8S/2424 Group 12.4 Section 12 Programmable Pulse Generator (PPG) Operation Figure 12.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.
PAGE 846
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 12.4.1 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 12.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH PO8 to PO15 m n m n Figure 12.
PAGE 847
H8S/2426, H8S/2426R, H8S/2424 Group 12.4.2 Section 12 Programmable Pulse Generator (PPG) Sample Setup Procedure for Normal Pulse Output Figure 12.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions [1] Set TGRA value [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] [1] Set TIOR to make TGRA an output compare register (with output disabled).
PAGE 848
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 12.4.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 12.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 12.
PAGE 849
H8S/2426, H8S/2426R, H8S/2424 Group 12.4.4 Section 12 Programmable Pulse Generator (PPG) Non-Overlapping Pulse Output During non-overlapping operation, transfer from NDR to PODR is performed as follows: • NDR bits are always transferred to PODR bits at compare match A. • At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 12.6 illustrates the non-overlapping pulse output operation.
PAGE 850
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) Figure 12.7 shows the timing of this operation. Compare match A Compare match B Write to NDR Write to NDR NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Do not write to NDR here Write to NDR here Figure 12.7 Non-Overlapping Operation and NDR Write Timing Page 820 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 851
H8S/2426, H8S/2426R, H8S/2424 Group 12.4.5 Section 12 Programmable Pulse Generator (PPG) Sample Setup Procedure for Non-Overlapping Pulse Output Figure 12.8 shows a sample procedure for setting up non-overlapping pulse output.
PAGE 852
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 12.4.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 12.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 65 95 00 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 12.
PAGE 853
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2.
PAGE 854
H8S/2426, H8S/2426R, H8S/2424 Group Section 12 Programmable Pulse Generator (PPG) 12.4.7 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 12.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 12.9.
PAGE 855
H8S/2426, H8S/2426R, H8S/2424 Group 12.4.8 Section 12 Programmable Pulse Generator (PPG) Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 12.11 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 12.
PAGE 856
Section 12 Programmable Pulse Generator (PPG) 12.5 Usage Notes 12.5.1 Module Stop Function Setting H8S/2426, H8S/2426R, H8S/2424 Group PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 23, Power-Down Modes. 12.5.2 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other peripheral functions such as the TPU.
PAGE 857
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) Section 13 8-Bit Timers (TMR) This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used to count external events and be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 13.
PAGE 858
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) Figure 13.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
PAGE 859
H8S/2426, H8S/2426R, H8S/2424 Group 13.2 Section 13 8-Bit Timers (TMR) Input/Output Pins Table 13.1 shows the pin configuration of the 8-bit timer module. Table 13.1 Pin Configuration Channel 0 1 13.
PAGE 860
Section 13 8-Bit Timers (TMR) 13.3.1 H8S/2426, H8S/2426R, H8S/2424 Group Timer Counter (TCNT) TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a clock. TCNT can be cleared by an external reset input or by a compare match signal A or B. Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR.
PAGE 861
H8S/2426, H8S/2426R, H8S/2424 Group 13.3.4 Section 13 8-Bit Timers (TMR) Timer Control Register (TCR) TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1.
PAGE 862
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.3.5 Timer Counter Control Register (TCCR) TCCR selects the TCNT internal clock source and controls the external reset input. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 R Reserved These bits are always read as 0 and cannot be modified. 3 TMRIS 0 R/W Timer Reset Input Select Selects the external reset input, in combination with the CCLR1 and CCLR0 bits in TCR. See table 13.2.
PAGE 863
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) Table 13.
PAGE 864
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) TCR TCCR Channel Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Bit 1 ICKS1 Bit 0 ICKS0 Description All 1 0 1 ⎯ ⎯ External clock, counted at rising edge 1 0 ⎯ ⎯ External clock, counted at falling edge 1 1 ⎯ ⎯ External clock, counted at both rising and falling edges Note: 13.3.6 * If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the TCNT_0 compare match signal, no incrementing clock is generated.
PAGE 865
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 5 OVF 0 R/(W)* Timer Overflow Flag [Setting condition] Set when TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF 4 ADTE 0 R/W A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A.
PAGE 866
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) • TCSR_1 Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* Compare Match Flag B [Setting condition] • Set when TCNT matches TCORB [Clearing conditions] 6 CMFA 0 R/(W)* • Cleared by reading CMFB when CMFB = 1, then writing 0 to CMFB • When DTC is activated by CMIB interrupt while DISEL bit of MRB in DTC is 0 Compare Match Flag A [Setting condition] • Set when TCNT matches TCORA [Clearing conditions] 5 OVF 0
PAGE 867
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) Bit Bit Name Initial Value R/W Description 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs.
PAGE 868
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.4 Operation 13.4.1 Pulse Output Figure 13.2 shows an example in which the 8-bit timer is used to generate a pulse output with a selected duty cycle. The control bits are set as follows: [1] In TCR, the CCLR1 bit is cleared to 0 and the CCLR0 bit is set to 1 so that TCNT is cleared at a TCORA compare match.
PAGE 869
H8S/2426, H8S/2426R, H8S/2424 Group 13.4.2 Section 13 8-Bit Timers (TMR) Reset Input Figure 13.3 shows an example in which the 8-bit timer is used to generate a pulse output with a selected delay in response to the TMRI input. The control bits are set as follows: [1] The CCLR0 bit in TCR is set to 1 and the TMRIS bit in TCCR is set to 1 so that TCNT is cleared at the high level of the TMRI input.
PAGE 870
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.5 Operation Timing 13.5.1 TCNT Incrementation Timing Figure 13.4 shows the count timing for internal clock input. Figure 13.5 shows the count timing for external clock signal. Note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The counter will not increment correctly if the pulse width is less than these values.
PAGE 871
H8S/2426, H8S/2426R, H8S/2424 Group 13.5.2 Section 13 8-Bit Timers (TMR) Timing of CMFA and CMFB Setting when Compare-Match Occurs The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare match signal is not generated until the next incrementation clock input. Figure 13.
PAGE 872
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.5.3 Timing of Timer Output when Compare-Match Occurs When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Figure 13.7 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 13.7 Timing of Timer Output 13.5.
PAGE 873
H8S/2426, H8S/2426R, H8S/2424 Group 13.5.5 Section 13 8-Bit Timers (TMR) Timing of TCNT External Reset TCNT is cleared at the rising edge, falling edge, low level, or high level of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR. The clear pulse width must be at least 1.5 states for a single edge and at least 2.5 states for both edges. Figure 13.9 shows the timing of this operation.
PAGE 874
Section 13 8-Bit Timers (TMR) 13.6 H8S/2426, H8S/2426R, H8S/2424 Group Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). In this case, the timer operates as below. 13.6.
PAGE 875
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.7 Interrupt Sources 13.7.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 13.4. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller.
PAGE 876
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.8 Usage Notes 13.8.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 13.11 shows this operation. TCNT write cycle by CPU T2 T1 φ TCNT address Address Internal write signal Counter clear signal TCNT N H'00 Figure 13.
PAGE 877
H8S/2426, H8S/2426R, H8S/2424 Group 13.8.2 Section 13 8-Bit Timers (TMR) Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 13.12 shows this operation. TCNT write cycle by CPU T2 T1 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 13.
PAGE 878
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) 13.8.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs as shown in figure 13.13. TCOR write cycle by CPU T2 T1 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Inhibited Figure 13.
PAGE 879
H8S/2426, H8S/2426R, H8S/2424 Group 13.8.4 Section 13 8-Bit Timers (TMR) Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 13.5. Table 13.5 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 13.8.
PAGE 880
H8S/2426, H8S/2426R, H8S/2424 Group Section 13 8-Bit Timers (TMR) Table 13.6 Switching of Internal Clock and TCNT Operation No.
PAGE 881
H8S/2426, H8S/2426R, H8S/2424 Group No. 4 Timing of Switchover by Means of Modifying CKS1, CKS0, ICKS1, and ICKS0 Bits Switching from high to high Section 13 8-Bit Timers (TMR) TCNT Clock Operation Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 13.8.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop.
PAGE 882
Section 13 8-Bit Timers (TMR) Page 852 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
PAGE 883
H8S/2426, H8S/2426R, H8S/2424 Group Section 14 Watchdog Timer (WDT) Section 14 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer.
PAGE 884
H8S/2426, H8S/2426R, H8S/2424 Group Overflow Interrupt control WOVI (interrupt request signal) Clock WDTOVF Internal reset signal* Clock select Reset control RSTCSR TCNT φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock sources TSCR Module bus Bus interface Internal bus Section 14 Watchdog Timer (WDT) WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the register sett
PAGE 885
H8S/2426, H8S/2426R, H8S/2424 Group 14.3 Section 14 Watchdog Timer (WDT) Register Descriptions The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 14.6.1, Notes on Register Access. • Timer counter (TCNT) • Timer control/status register (TCSR) • Reset control/status register (RSTCSR) 14.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable up-counter.
PAGE 886
H8S/2426, H8S/2426R, H8S/2424 Group Section 14 Watchdog Timer (WDT) Bit Bit Name Initial Value R/W Description 6 WT/IT 0 R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. 5 TME 0 R/W Timer Enable When this bit is set to 1, TCNT starts counting.
PAGE 887
H8S/2426, H8S/2426R, H8S/2424 Group 14.3.3 Section 14 Watchdog Timer (WDT) Reset Control/Status Register (RSTCSR) RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows.
PAGE 888
Section 14 Watchdog Timer (WDT) 14.4 Operation 14.4.1 Watchdog Timer Mode H8S/2426, H8S/2426R, H8S/2424 Group To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflow occurs.
PAGE 889
H8S/2426, H8S/2426R, H8S/2424 Group Section 14 Watchdog Timer (WDT) TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT WDTOVF signal 132 states*2 Internal reset signal*1 518 states Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0. Figure 14.2 Operation in Watchdog Timer Mode R01UH0310EJ0500 Rev. 5.
PAGE 890
H8S/2426, H8S/2426R, H8S/2424 Group Section 14 Watchdog Timer (WDT) 14.4.2 Interval Timer Mode To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1.
PAGE 891
H8S/2426, H8S/2426R, H8S/2424 Group 14.6 Usage Notes 14.6.1 Notes on Register Access Section 14 Watchdog Timer (WDT) The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction.
PAGE 892
H8S/2426, H8S/2426R, H8S/2424 Group Section 14 Watchdog Timer (WDT) TCNT write or Writing to RSTE bit in RSTCSR 15 Address: H'FFBC (TCNT) H'FFBE (RSTCSR) 8 7 H'5A 0 Write data TCSR write Address: H'FFBC (TCSR) 15 8 7 H'A5 0 Write data Writing 0 to WOVF bit in RSTCSR Address: H'FFBE (RSTCSR) 15 8 7 H'A5 0 H'00 Writing to RSTE bit in RSTCSR Address: H'FFBE (RSTCSR) 15 8 H'5A 7 0 Write data Figure 14.
PAGE 893
H8S/2426, H8S/2426R, H8S/2424 Group 14.6.2 Section 14 Watchdog Timer (WDT) Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this operation. TCNT write cycle T1 T2 Next cycle φ Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 14.
PAGE 894
Section 14 Watchdog Timer (WDT) 14.6.5 H8S/2426, H8S/2426R, H8S/2424 Group Internal Reset in Watchdog Timer Mode This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period.
PAGE 895
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Section 15 Serial Communication Interface (SCI, IrDA) This LSI has five independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication.
PAGE 896
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2426, H8S/2426R, H8S/2424 Group Asynchronous Mode • • • • • Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error • Average transfer rate generator (SCI_2 only): 115.152 or 460.606 kbps at 10.667-MHz operation 115.196, 460.
PAGE 897
H8S/2426, H8S/2426R, H8S/2424 Group Bus interface Section 15 Serial Communication Interface (SCI, IrDA) Module data bus RxD RDR TDR RSR TSR SCMR SSR SCR SMR SEMR BRR φ Baud rate generator Transmission/ reception control TxD Parity generation φ/4 φ/16 φ/64 Clock Parity check External clock SCK Internal data bus [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR:
PAGE 898
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the serial communication interface. Table 15.
PAGE 899
H8S/2426, H8S/2426R, H8S/2424 Group 15.3 Section 15 Serial Communication Interface (SCI, IrDA) Register Descriptions The SCI has the following registers. The serial mode register (SMR), serial status register (SSR), and serial control register (SCR) are described separately for normal serial communication interface mode and Smart Card interface mode because their bit functions partially differ.
PAGE 900
Section 15 Serial Communication Interface (SCI, IrDA) • • • • • • • • • • • • • • • • • • H8S/2426, H8S/2426R, H8S/2424 Group Receive shift register_3 (RSR_3) Transmit shift register_3 (TSR_3) Receive data register_3 (RDR_3) Transmit data register_3 (TDR_3) Serial mode register_3 (SMR_3) Serial control register_3 (SCR_3) Serial status register_3 (SSR_3) Smart card mode register_3 (SCMR_3) Bit rate register_3 (BRR_3) Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_
PAGE 901
H8S/2426, H8S/2426R, H8S/2424 Group 15.3.3 Section 15 Serial Communication Interface (SCI, IrDA) Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission.
PAGE 902
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting.
PAGE 903
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 GM 0 R/W GSM Mode When this bit is set to 1, the SCI operates in GSM mode. In GSM mode, the timing of the TEND setting is advanced by 11.0 etu (Elementary Time Unit: the time for transfer of 1 bit), and clock output control mode addition is performed. For details, refer to section 15.7.8, Clock Output Control.
PAGE 904
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 3 BCP1 0 R/W Basic Clock Pulse 1 and 0 2 BCP0 0 R/W These bits, in combination with the BCP2 bit in SCMR, select the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode.
PAGE 905
H8S/2426, H8S/2426R, H8S/2424 Group 15.3.6 Section 15 Serial Communication Interface (SCI, IrDA) Serial Control Register (SCR) SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer/receive clock source. For details on interrupt requests, refer to section 15.9, Interrupt Sources. Some bit functions of SCR differ in normal serial communication interface mode and Smart Card interface mode.
PAGE 906
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1.
PAGE 907
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Selects the clock source and SCK pin function. Asynchronous mode 00: On-chip baud rate generator SCK pin functions as I/O port 01: On-chip baud rate generator (Outputs a clock of the same frequency as the bit rate from the SCK pin.
PAGE 908
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0.
PAGE 909
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in Smart Card interface mode. 1 CKE1 0 R/W Clock Enable 1 and 0 0 CKE0 0 R/W Enables or disables clock output from the SCK pin. The clock output can be dynamically switched in GSM mode. For details, refer to section 15.7.8, Clock Output Control.
PAGE 910
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit functions of SSR differ in normal serial communication interface mode and Smart Card interface mode.
PAGE 911
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
PAGE 912
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 4 FER 0 R/(W)* Framing Error Indicates that a framing error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] • When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked.
PAGE 913
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing conditions] 1 MPB 0 R • When 0 is written to TDRE after reading TDRE = 1 • When the DMAC or DTC is activated by a TXI interrupt and writes data to TDR Multiprocessor Bit MPB stores the
PAGE 914
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Smart Card Interface Mode (When SMIF bit in SCMR is 1) Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] • When the TE bit in SCR is 0 • When data is transferred from TDR to TSR, and data writing to TDR is enabled.
PAGE 915
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error occurred while receiving and the reception has ended abnormally. [Setting condition] • When the next serial reception is completed while RDRF = 1 The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost.
PAGE 916
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 3 PER 0 R/(W)* Parity Error Indicates that a parity error occurred while receiving in asynchronous mode and the reception has ended abnormally. [Setting condition] • When a parity error is detected during reception If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set.
PAGE 917
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 TEND 1 R Transmit End This bit is set to 1 when no error signal has been sent back from the receiving end and the next transmit data is ready to be transferred to TDR.
PAGE 918
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.3.8 Smart Card Mode Register (SCMR) SCMR selects Smart Card interface mode and its format. Bit Bit Name Initial Value R/W Description 7 BCP2 1 R/W Basic Clock Pulse 2 Selects, in combination with the BCP1 and BCP0 bits in SMR, the number of basic clock cycles in a 1-bit transfer interval in Smart Card interface mode. For the settings, refer to section 15.3.5, Serial Mode Register (SMR).
PAGE 919
H8S/2426, H8S/2426R, H8S/2424 Group 15.3.9 Section 15 Serial Communication Interface (SCI, IrDA) Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 15.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode, clocked synchronous mode, and Smart Card interface mode.
PAGE 920
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.3 shows sample N settings in BRR in normal asynchronous mode. Table 15.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 15.6 shows sample N settings in BRR in clocked synchronous mode. Table 15.8 shows sample N settings in BRR in Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock cycles in a 1-bit transfer interval) can be selected.
PAGE 921
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 12.288 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.69 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 79 0.00 1 90 0.16 1 95 0.
PAGE 922
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Operating Frequency φ (MHz) 25 30 33 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 3 110 –0.02 3 132 0.13 3 145 0.33 150 3 80 0.47 3 97 –0.35 3 106 0.39 300 2 162 –0.15 2 194 0.16 2 214 –0.07 600 2 80 0.47 2 97 –0.35 2 106 0.39 1200 1 162 –0.15 1 194 0.16 1 214 –0.07 2400 1 80 0.47 1 97 –0.35 1 106 0.39 4800 0 162 –0.
PAGE 923
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 17.2032 537600 0 0 18 562500 0 0 19.
PAGE 924
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2426, H8S/2426R, H8S/2424 Group Table 15.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 17.2032 4.3008 268800 18 4.5000 281250 19.6608 4.9152 307200 20 5.0000 312500 25 6.
PAGE 925
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) n 8 10 16 N n N n N 20 n N 25 n N 30 n N 3 233 33 n N 110 250 3 124 ⎯ ⎯ 3 249 500 2 249 ⎯ ⎯ 3 124 ⎯ ⎯ 1k 2 124 ⎯ ⎯ 2 249 ⎯ ⎯ 3 97 3 116 3 128 2.
PAGE 926
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode) (when n = 0 and S = 372) Operating Frequency φ (MHz) 10.00 10.7136 13.00 14.2848 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 9600 0 1 30.00 0 1 25.00 0 1 8.99 0 1 0.00 Operating Frequency φ (MHz) 16.00 18.00 20.00 25.
PAGE 927
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.3.10 IrDA Control Register (IrCR) IrCR selects the function of SCI_0. Bit Bit Name Initial Value R/W Description 7 IrE 0 R/W IrDA Enable Specifies normal SCI mode or IrDA mode for SCI_0 input/output.
PAGE 928
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 IrRxINV 0 R/W IrRx Data Invert Specifies the logic level of the IrRxD output to be inverted. When inversion is performed, the high pulse width specified by bits 6 to 4 becomes the low pulse width.
PAGE 929
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Bit Bit Name Initial Value R/W Description 2 ACS2 0 R/W 1 ACS1 0 R/W Asynchronous clock source selection (valid when CKE1 = 1 in asynchronous mode) 0 ACS0 0 R/W Selects the clock source for the average transfer rate. The basic clock can be automatically set by selecting the average transfer rate in spite of the value of ABCS. 000: External clock input 001: Selects 115.
PAGE 930
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.4 Operation in Asynchronous Mode Figure 15.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level).
PAGE 931
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 932
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
PAGE 933
H8S/2426, H8S/2426R, H8S/2424 Group 15.4.3 Section 15 Serial Communication Interface (SCI, IrDA) Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
PAGE 934
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 15.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1.
PAGE 935
H8S/2426, H8S/2426R, H8S/2424 Group 15.4.5 Section 15 Serial Communication Interface (SCI, IrDA) Data Transmission (Asynchronous Mode) Figure 15.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
PAGE 936
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
PAGE 937
H8S/2426, H8S/2426R, H8S/2424 Group 15.4.6 Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Reception (Asynchronous Mode) Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
PAGE 938
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2426, H8S/2426R, H8S/2424 Group Table 15.11 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.9 shows a sample flowchart for serial data reception.
PAGE 939
H8S/2426, H8S/2426R, H8S/2424 Group Initialization Section 15 Serial Communication Interface (SCI, IrDA) [1] Start of reception [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error handling and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error.
PAGE 940
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 15.9 Sample Serial Reception Data Flowchart (2) Page 910 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 941
H8S/2426, H8S/2426R, H8S/2424 Group 15.5 Section 15 Serial Communication Interface (SCI, IrDA) Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
PAGE 942
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB= 1) ID transmission cycle = receiving station specification (MPB= 0) Data transmission cycle = data transmission to receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 15.
PAGE 943
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
PAGE 944
Section 15 Serial Communication Interface (SCI, IrDA) 15.5.2 H8S/2426, H8S/2426R, H8S/2424 Group Multiprocessor Serial Data Reception Figure 15.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time.
PAGE 945
H8S/2426, H8S/2426R, H8S/2424 Group 1 Start bit 0 Section 15 Serial Communication Interface (SCI, IrDA) Data (ID1) MPB D0 D1 D7 1 Stop bit Start bit 1 0 Data (Data1) MPB D0 D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt handling routine If not this station’s ID, RXI interrupt request is MPIE bit is set to 1 not generated, and RDR again
PAGE 946
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1.
PAGE 947
H8S/2426, H8S/2426R, H8S/2424 Group [5] Section 15 Serial Communication Interface (SCI, IrDA) Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) R01UH0310EJ0500 Rev. 5.
PAGE 948
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.6 Operation in Clocked Synchronous Mode Figure 15.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character of communication data consists of 8-bit data. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
PAGE 949
H8S/2426, H8S/2426R, H8S/2424 Group 15.6.2 Section 15 Serial Communication Interface (SCI, IrDA) SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 15.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1.
PAGE 950
Section 15 Serial Communication Interface (SCI, IrDA) 15.6.3 H8S/2426, H8S/2426R, H8S/2424 Group Serial Data Transmission (Clocked Synchronous Mode) Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
PAGE 951
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Transfer direction Serial clock Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode R01UH0310EJ0500 Rev. 5.
PAGE 952
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? [3] Yes Read TEND flag in SSR [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin.
PAGE 953
H8S/2426, H8S/2426R, H8S/2424 Group 15.6.4 Section 15 Serial Communication Interface (SCI, IrDA) Serial Data Reception (Clocked Synchronous Mode) Figure 15.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2.
PAGE 954
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] Start of reception [2] Read ORER flag in SSR Yes [3] ORER = 1? No Error processing (Continued below) Read RDRF flag in SSR [4] No RDRF = 1? Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
PAGE 955
H8S/2426, H8S/2426R, H8S/2424 Group 15.6.5 Section 15 Serial Communication Interface (SCI, IrDA) Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) Figure 15.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI is initialized.
PAGE 956
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations.
PAGE 957
H8S/2426, H8S/2426R, H8S/2424 Group 15.7 Section 15 Serial Communication Interface (SCI, IrDA) Operation in Smart Card Interface Mode The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 15.7.1 Pin Connection Example Figure 15.
PAGE 958
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.7.2 Data Format (Except for Block Transfer Mode) Figure 15.22 shows the transfer data format in Smart Card interface mode. • One frame consists of 8-bit data plus a parity bit in asynchronous mode. • In transmission, a guard time of at least 2 etu (Elementary Time Unit: time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame.
PAGE 959
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) As in the above sample start character, with the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to select even parity mode.
PAGE 960
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.4 H8S/2426, H8S/2426R, H8S/2424 Group Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate (fixed at 16 times in normal asynchronous mode) as determined by bits BCP2 to BCP0.
PAGE 961
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 372 clocks 186 clocks 0 185 185 371 0 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 15.25 Receive Data Sampling Timing in Smart Card Mode (Using Clock of 372 Times the Bit Rate) R01UH0310EJ0500 Rev. 5.
PAGE 962
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.5 H8S/2426, H8S/2426R, H8S/2424 Group Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. 1. Clear the TE and RE bits in SCR to 0. 2. Clear the error flags ERS, PER, and ORER in SSR to 0. 3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and the BCP2 bit in SCMR. Set the PE bit to 1. 4.
PAGE 963
H8S/2426, H8S/2426R, H8S/2424 Group 15.7.6 Section 15 Serial Communication Interface (SCI, IrDA) Data Transmission (Except for Block Transfer Mode) As data transmission in Smart Card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). Figure 15.26 illustrates the retransfer operation when the SCI is in transmit mode. 1.
PAGE 964
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Transfer frame n+1 Retransferred frame nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 TDRE Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR from TDR TEND [2] [4] FER/ERS [1] [3] Figure 15.26 Retransfer Operation in SCI Transmit Mode The timing for setting the TEND flag depends on the value of the GM bit in SMR.
PAGE 965
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Start Initialization Start transmission ERS = 0? No Yes Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted ? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 15.28 Example of Transmission Processing Flow R01UH0310EJ0500 Rev. 5.
PAGE 966
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.7 H8S/2426, H8S/2426R, H8S/2424 Group Serial Data Reception (Except for Block Transfer Mode) Data reception in Smart Card interface mode uses the same operation procedure as for normal serial communication interface mode. Figure 15.29 illustrates the retransfer operation when the SCI is in receive mode. 1. If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
PAGE 967
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) nth transfer frame Transfer frame n+1 Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4 RDRF [2] [4] [1] [3] PER Figure 15.
PAGE 968
Section 15 Serial Communication Interface (SCI, IrDA) 15.7.8 H8S/2426, H8S/2426R, H8S/2424 Group Clock Output Control When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled.
PAGE 969
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) When Changing from Smart Card Interface Mode to Software Standby Mode: 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. 2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation.
PAGE 970
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.8 IrDA Operation When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to implement infrared transmission/reception conforming to the IrDA specification version 1.0 system.
PAGE 971
H8S/2426, H8S/2426R, H8S/2424 Group (1) Section 15 Serial Communication Interface (SCI, IrDA) Transmission In transmission, the output signal (UART frame) from the SCI is converted to an IR frame by the IrDA interface (see figure 15.34). When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one bit) is output (initial value). The high-level pulse can be varied according to the setting of bits IrCKS2 to IrCKS0 in IrCR.
PAGE 972
Section 15 Serial Communication Interface (SCI, IrDA) (2) H8S/2426, H8S/2426R, H8S/2424 Group Reception In reception, IR frame data is converted to a UART frame by the IrDA interface, and input to the SCI. When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified as a 0 signal. (3) High Pulse Width Selection Table 15.
PAGE 973
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.12 Settings of IrCKS2 to IrCKS0 Bits Bit Rate (bps) (Above)/Bit Period × 3/16 (µs) (Below) Operating Frequency φ (MHz) 2400 9600 19200 38400 57600 115200 78.13 19.53 9.77 4.88 3.26 1.63 8 100 100 100 100 100 100 9.8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12.
PAGE 974
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2426, H8S/2426R, H8S/2424 Group 15.9 Interrupt Sources 15.9.1 Interrupts in Normal Serial Communication Interface Mode Table 15.13 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated.
PAGE 975
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Table 15.
PAGE 976
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.9.2 Interrupts in Smart Card Interface Mode Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt (TEI) request cannot be used in this mode. Table 15.
PAGE 977
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) When performing transfer using the DTC or DMAC, it is essential to set and enable the DTC or DMAC before carrying out SCI setting. For details on the DTC or DMAC setting procedures, refer to section 9, Data Transfer Controller (DTC) or section 7, DMA Controller (DMAC). In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1.
PAGE 978
Section 15 Serial Communication Interface (SCI, IrDA) 15.10 H8S/2426, H8S/2426R, H8S/2424 Group Usage Notes 15.10.1 Module Stop Function Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 23, Power-Down Modes. 15.10.
PAGE 979
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) 15.10.5 Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag.
PAGE 980
Section 15 Serial Communication Interface (SCI, IrDA) H8S/2426, H8S/2426R, H8S/2424 Group 15.10.7 Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before setting the module stop state or making a transition to software standby mode. TSR, TDR, and SSR are reset. The output pin states in the module stop state or software standby mode depend on the port settings, and become high-level output after the relevant mode is cleared.
PAGE 981
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) All data transmitted? No [1] Yes Read TEND flag in SSR TEND = 1 No Yes TE = 0 [2] Transition to software standby mode [3] [1] Data being transmitted is interrupted.
PAGE 982
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Port Start Stop Port input/output SCI TxD output High output SCI TxD output Port Figure 15.
PAGE 983
H8S/2426, H8S/2426R, H8S/2424 Group Section 15 Serial Communication Interface (SCI, IrDA) Read RDRF flag in SSR RDRF = 1 No [1] [1] Receive data being received becomes invalid. [2] [2] Includes setting of module stop state. Yes Read receive data in RDR RE = 0 Transition to software standby mode Exit from software standby mode Change operating mode? No Yes Initialization RE = 1 Figure 15.
PAGE 984
Section 15 Serial Communication Interface (SCI, IrDA) Page 954 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
PAGE 985
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Section 16 I2C Bus Interface 2 (IIC2) This LSI has a four-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the NXP I2C bus (inter-IC bus) interface functions (Rev. 0.3) for standard-mode and fast-mode. The register configuration that controls the I2C bus differs partly from the NXP configuration, however. Figure 16.1 shows a block diagram of the I2C bus interface 2. Figure 16.
PAGE 986
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Transfer clock generation circuit Transmission/ reception control circuit Output control SCL ICCRA ICCRB ICMR Internal data bus Noise canceler ICDRT Output control SDA ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICEIR Interrupt generator [Legend] ICCRA: ICCRB: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: Interrupt request 2 I C bus control register
PAGE 987
H8S/2426, H8S/2426R, H8S/2424 Group Vcc SCL in Section 16 I2C Bus Interface 2 (IIC2) Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL SDA (Master) SCL SDA SDA out SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 16.2 External Circuit Connections of I/O Pins 16.2 Input/Output Pins Table 16.1 shows the pin configuration of the I2C bus interface 2. Table 16.
PAGE 988
Section 16 I2C Bus Interface 2 (IIC2) 16.3 H8S/2426, H8S/2426R, H8S/2424 Group Register Descriptions The I2C bus interface has the following registers.
PAGE 989
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Channel 2 • • • • • • • • • I2C bus control register A_2 (ICCRA_2) I2C bus control register B_2 (ICCRB_2) I2C bus mode register_2 (ICMR_2) I2C bus interrupt enable register_2 (ICIER_2) I2C bus status register_2 (ICSR_2) Slave address register_2 (SAR_2) I2C bus transmit data register_2 (ICDRT_2) I2C bus receive data register_2 (ICDRR_2) I2C bus shift register_2 (ICDRS_2) Channel 3 • • • • • • • • • I2C bus control register A_3 (IC
PAGE 990
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) 16.3.1 I2C Bus Control Register A (ICCRA) ICCRA is an 8-bit readable/writable register that enables or disables the I2C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 0: Disables SCL/SDA outputs. (Inputs to SCL/SDA are available.
PAGE 991
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Table 16.
PAGE 992
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) 16.3.2 I2C Bus Control Register B (ICCRB) ICCRB is an 8-bit readable/writable register that issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in I2C control. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start and stop conditions in master mode.
PAGE 993
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 IICRST 0 R/W IIC Control Part Reset 2 This bit resets control parts except for I C registers. If this bit is set to 1 when hang-up is occurred because of communication failure during 2 2 I C operation, I C control part can be reset without setting ports and initializing registers. 0 ⎯ 1 ⎯ Reserved This bit is always read as 1. 16.3.
PAGE 994
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. When read, the remaining number of transfer bits is indicated. The data is transferred with one addition acknowledge bit. Bit BC2 to BC0 settings should be made during an interval between transfer frames.
PAGE 995
H8S/2426, H8S/2426R, H8S/2424 Group 16.3.4 Section 16 I2C Bus Interface 2 (IIC2) I2C Bus Interrupt Enable Register (ICIER) ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received.
PAGE 996
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, AL, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled. 1: NACK receive interrupt request (NAKI) is enabled.
PAGE 997
H8S/2426, H8S/2426R, H8S/2424 Group 16.3.5 Section 16 I2C Bus Interface 2 (IIC2) I2C Bus Status Register (ICSR) ICSR is an 8-bit readable/writable register that performs confirmation of interrupt request flags and status. Bit Bit Name Initial Value R/W 7 TDRE 0 R/W Description Transmit Data Register Empty [Setting condition] 6 TEND 0 R/W • When data is transferred from ICDRT to ICDRS and ICDRT becomes empty. • When TRS has been set.
PAGE 998
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1. [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1. Stop Condition Detection Flag [Setting condition] • When a stop condition is detected after frame transfer.
PAGE 999
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 1 AAS 0 R/W Slave Address Recognition Flag In slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting condition] • When the slave address is detected in slave receive mode. • When the general call address is detected in slave receive mode.
PAGE 1000
Section 16 I2C Bus Interface 2 (IIC2) 16.3.7 H8S/2426, H8S/2426R, H8S/2424 Group I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the I2C bus shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
PAGE 1001
H8S/2426, H8S/2426R, H8S/2424 Group 16.4 Operation 16.4.1 I2C Bus Format Section 16 I2C Bus Interface 2 (IIC2) Figure 16.3 shows the I2C bus formats. Figure 16.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
PAGE 1002
Section 16 I2C Bus Interface 2 (IIC2) H8S/2426, H8S/2426R, H8S/2424 Group Legend: S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receiving device drives SDA to low. DATA: Transferred data P: 16.4.2 Stop condition.
PAGE 1003
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) SCL (master output) 1 2 3 4 5 6 SDA (master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (slave output) A TDRE TEND Address + R/W ICDRT ICDRS Data 1 Address + R/W User [2] Instruction of start processing condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte). [3] Write data to ICDRT (first byte).
PAGE 1004
Section 16 I2C Bus Interface 2 (IIC2) 16.4.3 H8S/2426, H8S/2426R, H8S/2424 Group Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2.
PAGE 1005
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Master transmit mode SCL (master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (master output) SDA (slave output) 9 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 16.7 Master Receive Mode Operation Timing 1 R01UH0310EJ0500 Rev. 5.
PAGE 1006
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) SCL (master output) 9 SDA (master output) A SDA (slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR User processing Data n Data n-1 [5] Read ICDRR after setting RCVD. [6] Issue stop condition [7] Read ICDRR and clear RCVD [8] Set slave receive mode Figure 16.8 Master Receive Mode Operation Timing 2 16.4.
PAGE 1007
H8S/2426, H8S/2426R, H8S/2424 Group Slave receive mode SCL (master output) Section 16 I2C Bus Interface 2 (IIC2) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (master output) 9 1 A SCL (slave output) SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 7 Bit 0 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1). [2] Write data to ICDRT (data 2). [2] Write data to ICDRT (data 3). Figure 16.
PAGE 1008
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (master output) 9 SDA (master output) A 1 2 3 4 5 6 7 8 9 A/A SCL (slave output) SDA (slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 16.
PAGE 1009
H8S/2426, H8S/2426R, H8S/2424 Group 16.4.5 Section 16 I2C Bus Interface 2 (IIC2) Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCRA to 1. Set the MLS and WAIT bits in ICMR and the CKS3 to CKS0 bits in ICCRA to 1.
PAGE 1010
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) SCL (master output) 9 SDA (master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (slave output) SDA (slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [7] Read ICDRR. [4] Read ICDRR (dummy read). Figure 16.
PAGE 1011
H8S/2426, H8S/2426R, H8S/2424 Group 16.4.6 Section 16 I2C Bus Interface 2 (IIC2) Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree.
PAGE 1012
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Start Initialize Read BBSY in ICCRB [1] Test the status of the SCL and SDA lines. [2] Select master transmit mode. [3] Start condition issuance. [4] Select transmit data for the first byte (slave address + R/W). [5] Wait for 1 byte to be transmitted. [6] Test the acknowledge bit, transferred from the specified slave device. [7] Set transmit data for the second and subsequent data (except for the final byte).
PAGE 1013
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmitting device.* [3] Dummy read ICDDR.* [4] Wait for 1 byte to be received. [5] Check if the (last receive - 1). [6] Read the receive data. [7] Set acknowledge of the final byte. Disable continuous receive (RCVD = 1). [8] Read receive data of (final byte - 1).
PAGE 1014
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) [1] Clear the flag AAS. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of the transmit data. Read TDRE in ICSR No [5] Wait the transmission end of the last byte. [3] TDRE=1 ? Yes No [6] Clear the flag TEND. [7] Set slave receive mode. End of transmission? Yes [2] Set transmit data for ICDRT (except for the last data).
PAGE 1015
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) Slave receive mode Read RDRF in ICSR No RDRF=1 ? Yes Read AAS in ICSR No Set RIE = 0 in ICIER AAS=1 ? [2] Clear the flag AAS. Yes Clear AAS in ICSR [12] Read STOP in ICSR No [1] [1] Determination of slave address* Use receive-data-full interrupts to determine whether the slave address matches. • If the slave address did match (AAS = 1), execute steps [2] to [11].
PAGE 1016
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) 16.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each interrupt request. Table 16.
PAGE 1017
H8S/2426, H8S/2426R, H8S/2424 Group 16.6 Section 16 I2C Bus Interface 2 (IIC2) Bit Synchronous Circuit In master mode, • When SCL is driven to low by the slave device • When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up resistance) This module has a possibility that high level period may be short in the two states described above. Therefore it monitors SCL and communicates by bit with synchronization. Figure 16.
PAGE 1018
Section 16 I2C Bus Interface 2 (IIC2) 16.7 H8S/2426, H8S/2426R, H8S/2424 Group Usage Notes 1. Issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check SCLO in the I2C control register B (IICRB) to confirm the fall of the ninth clock. When the start/stop conditions are issued (retransmitted) at the specific timing under the following condition (i) or (ii), such conditions may not be output successfully. This does not occur in other cases.
PAGE 1019
H8S/2426, H8S/2426R, H8S/2424 Group Section 16 I2C Bus Interface 2 (IIC2) ⎯ Write 0 to BBSY and SCP in ICCRB to issue the stop condition when SDA = low in master transmission or master reception mode and this module is the only module which pulls SCL low. BBSY is cleared to 0 when the stop condition (SCL = high and SDA rising) is output. 5.
PAGE 1020
Section 16 I2C Bus Interface 2 (IIC2) H8S/2426, H8S/2426R, H8S/2424 Group 8. Notes on Changing from Master Transmit Mode to Master Receive Mode If TRS is cleared to 0 before the falling edge of the 9th clock in master transmit mode when master transmit mode is changed to master receive mode, this module outputs the receive clock in synchronization with the internal clock whether ICDRR is read (dummy read) or not.
PAGE 1021
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Section 17 A/D Converter This LSI includes two units (units 0 and 1) of successive approximation type 10-bit A/D converter. In the H8S/2426 group and H8S/2426R group, the A/D converter units 0 and 1 allow up to eight analog input channels to be selected. In the H8S/2424 group, unit 0 allows up to eight analog input channels to be selected while unit 1 allows up to two channels. Figures 17.1 and 17.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Internal data bus AVSS Bus interface ADCR_0 ADCSR_0 ADDRH_0 ADDRG_0 ADDRF_0 ADDRE_0 ADDRD_0 ADDRC_0 ADDRB_0 10-bit A/D Vref ADDRA_0 AVCC Successive approximation register Module data bus AN0 + AN1 AN2 Multiplexer – AN3 AN4 AN5 AN6 Comparator Control circuit Sample-andhold circuit AN7 ADI0 interrupt signal ADTRG0-A ADTRG0-B [Legend] ADCR_0: ADCSR_0: ADDRA_0: ADDRB_0: ADDRC_0: Conversion start trigger from TPU (units 0,
PAGE 1023
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Internal data bus AVSS Bus interface ADCR_1 ADCSR_1 ADDRH_1 ADDRG_1 ADDRF_1 ADDRE_1 ADDRD_1 ADDRC_1 ADDRB_1 10-bit A/D Vref ADDRA_1 AVCC Successive approximation register Module data bus AN8* + AN9* – Multiplexer AN10* AN11* AN12 AN13 Comparator Control circuit Sample-andhold circuit AN14* AN15* ADI1 interrupt signal ADTRG1-A [Legend] ADCR_1: ADCSR_1: ADDRA_1: ADDRB_1: ADDRC_1: Conversion start trigger from TPU (units
PAGE 1024
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter 17.2 Input/Output Pins Tables 17.1 and 17.2 show the pin configuration of the A/D converter. Table 17.
PAGE 1025
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Table 17.2 Pin Configuration (H8S/2424 Group) Unit Abbr.
PAGE 1026
Section 17 A/D Converter 17.3 H8S/2426, H8S/2426R, H8S/2424 Group Register Descriptions The A/D converter has the following registers.
PAGE 1027
H8S/2426, H8S/2426R, H8S/2424 Group 17.3.1 Section 17 A/D Converter A/D Data Registers A to H (ADDRA to ADDRH) There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in tables 17.3 and 17.4. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width.
PAGE 1028
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Table 17.
PAGE 1029
H8S/2426, H8S/2426R, H8S/2424 Group 17.3.2 Section 17 A/D Converter A/D Control/Status Register for Unit 0 (ADCSR_0) ADCSR_0 controls A/D conversion operations. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* A/D End Flag Description A status flag that indicates the end of A/D conversion.
PAGE 1030
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Bit Bit Name Initial Value R/W Description 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.
PAGE 1031
H8S/2426, H8S/2426R, H8S/2424 Group 17.3.3 Section 17 A/D Converter A/D Control/Status Register for Unit 1 (ADCSR_1) ADCSR_1 controls A/D conversion operations. Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* A/D End Flag Description A status flag that indicates the end of A/D conversion.
PAGE 1032
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter • H8S/2426 Group and H8S/2426R Group Bit Bit Name Initial Value R/W Description 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.
PAGE 1033
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter • H8S/2424 Group Bit Bit Name Initial Value R/W Description 3 2 1 0 CH3 CH2 CH1 CH0 0 0 0 0 R/W R/W R/W R/W Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR.
PAGE 1034
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter 17.3.4 A/D Control Register (ADCR_0) Unit 0 ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 and Extended Trigger Select 6 TRGS0 0 R/W 0 EXTRGS 0 R/W These bits enable or disable the start of A/D conversion by a trigger signal.
PAGE 1035
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Bit Bit Name Initial Value R/W Description 3 CKS1 0 R/W Clock Select 1 and 0 2 CKS0 0 R/W These bits select the A/D conversion clock (ADCLK) and specify the A/D conversion time in combination with the EXCKS bit. First select the A/D conversion time while ADST = 0 in ADCSR and then set the mode of A/D conversion. Before entering software standby mode or module stop state, set these bits to B'11.
PAGE 1036
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter 17.3.5 A/D Control Register (ADCR_1) Unit 1 ADCR enables A/D conversion to be started by an external trigger input. Bit Bit Name Initial Value R/W Description 7 TRGS1 0 R/W Timer Trigger Select 1 and 0 and Extended Trigger Select 6 TRGS0 0 R/W 0 EXTRGS 0 R/W These bits enable or disable the start of A/D conversion by a trigger signal.
PAGE 1037
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Bit Bit Name Initial Value R/W Description 3 CKS1 0 R/W Clock Select 1 and 0 2 CKS0 0 R/W These bits select the A/D conversion clock (ADCLK) and specify the A/D conversion time in combination with the EXCKS bit. First select the A/D conversion time while ADST = 0 in ADCSR and then set the mode of A/D conversion. Before entering software standby mode or module stop state, set these bits to B'11.
PAGE 1038
Section 17 A/D Converter 17.4 H8S/2426, H8S/2426R, H8S/2424 Group Operation The A/D converter has two operating modes: single mode and scan mode. First select the clock for A/D conversion (ADCLK). When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 17.4.
PAGE 1039
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Set* ADIE Set* ADST Set* A/D conversion start Clear* Clear* ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Waiting for conversion Waiting for conversion A/D conversion 1 Channel 2 (AN2) operation state Waiting for conversion Channel 3 (AN3) operation state Waiting for conversion Waiting for conversion A/D conversion 2 Waiting for conversion ADDRA Reading A/D conversion result A/D conversion result 1 ADDRB Re
PAGE 1040
Section 17 A/D Converter 17.4.2 H8S/2426, H8S/2426R, H8S/2424 Group Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight* channels. Two types of scan mode are provided, that is, continuous scan mode where A/D conversion is repeatedly performed and one-cycle scan mode where A/D conversion is performed for the specified channels for one cycle. (1) Continuous Scan Mode 1.
PAGE 1041
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter A/D conversion consecutive execution Clear*1 Set*1 ADST Clear*1 ADF Channel 0 (AN0) operation state Waiting for conversion A/D conversion 1 Channel 1 (AN1) operation state Waiting for conversion Channel 2 (AN2) operation state Waiting for conversion Channel 3 (AN3) operation state Waiting for conversion A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion A/D conversion 3 Waiting for
PAGE 1042
Section 17 A/D Converter (2) H8S/2426, H8S/2426R, H8S/2424 Group One-Cycle Scan Mode 1. Set the ADSTCLR bit in ADCR to 1. 2. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger input, A/D conversion starts on the first channel in the specified channel group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels (SCANE and SCANS = B'11) can be selected.
PAGE 1043
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter A/D conversion one-cycle execution Set * ADST Clear* ADF A/D conversion time Channel 4 (AN4) Waiting for conversion operation state Channel5 (AN5) operation state Channel 6 (AN6) operation state Waiting for conversion A/D conversion 1 Waiting for conversion Waiting for conversion A/D conversion 2 Waiting for conversion Waiting for conversion A/D conversion 3 Channel 7 (AN7) operation state Waiting for conversion Transfer ADDRE A/D c
PAGE 1044
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter 17.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 17.6 shows the A/D conversion timing. Tables 17.5 and 17.6 show the A/D conversion time. As shown in figure 17.
PAGE 1045
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Table 17.5 A/D Conversion Characteristics (EXCKS = 0) CKS1 = 0 CKS1 = 1 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time tD 4 ⎯ 10 4 ⎯ 8 3 ⎯ 7 Input sampling time tSPL ⎯ 156 ⎯ ⎯ 78 ⎯ ⎯ 39 ⎯ A/D conversion time tCONV 262 ⎯ 268 134 ⎯ 138 69 ⎯ 73 Note: Values in the table are the number of states. Table 17.
PAGE 1046
Section 17 A/D Converter 17.4.4 H8S/2426, H8S/2426R, H8S/2424 Group External Trigger Input Timing A/D conversion can be externally triggered. For unit 0, an external trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 or B'001 in ADCR_0. For unit 1, an external trigger is input from the ADTRG1 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 in ADCR_1.
PAGE 1047
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter φ ADTRG0 Internal trigger signal ADST A/D conversion Figure 17.8 External Trigger Input Timing when Multiple Units Start Simultaneously (TRSG1, TRGS0, and EXTRGS = B'111) 17.5 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests.
PAGE 1048
Section 17 A/D Converter 17.6 H8S/2426, H8S/2426R, H8S/2424 Group A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes. • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.9).
PAGE 1049
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 17.9 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 17.
PAGE 1050
Section 17 A/D Converter 17.7 Usage Notes 17.7.1 Module Stop Function Setting H8S/2426, H8S/2426R, H8S/2424 Group Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state.
PAGE 1051
H8S/2426, H8S/2426R, H8S/2424 Group 17.7.4 Section 17 A/D Converter Permissible Signal Source Impedance This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
PAGE 1052
Section 17 A/D Converter 17.7.5 H8S/2426, H8S/2426R, H8S/2424 Group Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, acting as antennas. 17.7.
PAGE 1053
H8S/2426, H8S/2426R, H8S/2424 Group 17.7.7 Section 17 A/D Converter Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values.
PAGE 1054
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter AVCC Vref 100 Ω Rin* 2 *1 AN0 to AN15* 3 *1 0.1 µF AVSS Notes: Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance 3. The H8S/2424 group has only AN0 to AN7, AN11, and AN12 as analog input pins. Figure 17.12 Example of Analog Input Protection Circuit Table 17.9 Analog Pin Specifications Item Min. Max.
PAGE 1055
H8S/2426, H8S/2426R, H8S/2424 Group 17.7.9 Section 17 A/D Converter Concurrent Operation of Two A/D Converters When operating two A/D converters concurrently, if conversion by the two converters starts at different times, the accuracy of conversion may be affected by crosstalk between the two converters. When converter Y starts A/D conversion during the period indicated by TX-Y in figure 17.
PAGE 1056
H8S/2426, H8S/2426R, H8S/2424 Group Section 17 A/D Converter 17.7.10 Notes on Start of A/D Conversion by Conversion Start Trigger from TPU (Units 0 and 1) When A/D conversion starts by a conversion start trigger from the TPU, the register settings of the TPU and A/D converters must be checked so that A/D conversion does not start at unintended timing.
PAGE 1057
H8S/2426, H8S/2426R, H8S/2424 Group Section 18 D/A Converter Section 18 D/A Converter 18.1 Features D/A converter features are listed below. • • • • • • 8-bit resolution Output channels: Two channels Maximum conversion time of 10 µs (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop state can be set. R01UH0310EJ0500 Rev. 5.
PAGE 1058
Module data bus Bus interface H8S/2426, H8S/2426R, H8S/2424 Group Section 18 D/A Converter Internal data bus DA2 D/A DACR23 8-bit DA3 DADR3 AVcc DADR2 Vref AVss Control circuit [Legend] DADR2: D/A data register 2 DADR3: D/A data register 3 DACR23: D/A control register 23 Figure 18.1 Block Diagram of D/A Converter Page 1028 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1059
H8S/2426, H8S/2426R, H8S/2424 Group 18.2 Section 18 D/A Converter Input/Output Pins Table 18.1 shows the pin configuration of the D/A converter. Table 18.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin Analog ground pin AVCC Input Analog power AVSS Input Analog ground Reference voltage pin Vref Input Reference voltage of D/A converter Analog output pin 2 DA2 Output Channel 2 analog output Analog output pin 3 DA3 Output Channel 3 analog output R01UH0310EJ0500 Rev.
PAGE 1060
H8S/2426, H8S/2426R, H8S/2424 Group Section 18 D/A Converter 18.3 Register Descriptions The D/A converter has the following registers. • D/A data register 2 (DADR2) • D/A data register 3 (DADR3) • D/A control register 23 (DACR23) 18.3.1 D/A Data Registers 2 and 3 (DADR2 and DADR3) DADR2 and DADR3 are 8-bit readable/writable registers that store data for conversion. Whenever analog output is enabled, the values in DADR are converted and output to the analog output pins. 18.3.
PAGE 1061
H8S/2426, H8S/2426R, H8S/2424 Group Section 18 D/A Converter Bit Bit Name Initial Value R/W Description 5 DAE 0 R/W D/A Enable This bit is used together with the DAOE2 and DAOE3 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 2 and 3 D/A conversions are controlled independently. When the DAE bit is set to 1, channel 2 and 3 D/A conversions are controlled together. Output of conversion results is always controlled independently by the DAOE2 and DAOE3 bits.
PAGE 1062
H8S/2426, H8S/2426R, H8S/2424 Group Section 18 D/A Converter Table 18.2 Control of D/A Conversion Bit 5 DAE Bit 7 Bit 6 DAOE3 DAOE2 Description 0 0 0 D/A conversion disabled 1 Channel 2 D/A conversion enabled, and channel 3 D/A conversion disabled. Channel 2 analog output (DA2) enabled, and channel 3 analog output (DA3) disabled. 1 0 Channel 2 D/A conversion disabled, and channel 3 D/A conversion enabled. Channel 2 analog output (DA2) disabled, channel 3 analog output (DA3) enabled.
PAGE 1063
H8S/2426, H8S/2426R, H8S/2424 Group 18.4 Section 18 D/A Converter Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When DAOE bit in DACR23 is set to 1, D/A conversion is enabled and the conversion result is output. The following shows an example of D/A conversion on channel 2. Figure 18.2 shows the timing of this operation. 1. Write the conversion data to DADR2. 2. Set the DAOE2 bit in DACR23 to 1. D/A conversion is started.
PAGE 1064
H8S/2426, H8S/2426R, H8S/2424 Group Section 18 D/A Converter DADR2 write cycle DADR2 write cycle DACR23 write cycle DACR23 write cycle φ Address DADR2 Conversion data 1 Conversion data 2 DAOE2 DA2 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV [Legend] tDCONV: D/A conversion time Figure 18.2 Example of D/A Converter Operation Page 1034 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1065
H8S/2426, H8S/2426R, H8S/2424 Group 18.5 Usage Notes 18.5.1 Module Stop Function Setting Section 18 D/A Converter D/A converter operation can be disabled or enabled using the module stop control register. The initial setting is for the D/A converter to be halted. Register access is enabled by clearing the module stop state. For details, see section 23, Power-Down Modes. 18.5.
PAGE 1066
Section 18 D/A Converter Page 1036 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
PAGE 1067
H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Section 19 Synchronous Serial Communication Unit (SSU) This LSI has one channel of synchronous serial communication unit (SSU). The SSU has master mode in which this LSI outputs clocks as a master device for synchronous serial communication and slave mode in which clocks are input from an external device for synchronous serial communication.
PAGE 1068
H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Module data bus SSCRH Bus interface Figure 19.1 shows a block diagram of the SSU.
PAGE 1069
H8S/2426, H8S/2426R, H8S/2424 Group 19.2 Section 19 Synchronous Serial Communication Unit (SSU) Input/Output Pins Table 19.1 shows the SSU pin configuration. Table 19.1 Pin Configuration Channel Symbol I/O Function 0 SSCK0 I/O SSU clock input/output SSI0 I/O SSU data input/output SSO0 I/O SSU data input/output SCS0 I/O SSU chip select input/output Note: 19.3 * Because channel numbers are omitted in later descriptions, these are shown SSCK, SSI, SSO, and SCS.
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Section 19 Synchronous Serial Communication Unit (SSU) 19.3.1 H8S/2426, H8S/2426R, H8S/2424 Group SS Control Register H (SSCRH) SSCRH specifies master/slave device selection, bidirectional mode enable, SSO pin output value selection, SSCK pin selection, and SCS pin selection. Bit Bit Name Initial Value R/W Description 7 MSS 0 R/W Master/Slave Device Select Selects that this module is used in master mode or slave mode. When master mode is selected, transfer clocks are output from the SSCK pin.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 4 SOL 0 R/W Serial Data Output Value Select The serial data output retains its level of the last bit after completion of transmission. The output level before or after transmission can be specified by setting this bit. When specifying the output level, use the MOV instruction after clearing the SOLP bit to 0.
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Section 19 Synchronous Serial Communication Unit (SSU) 19.3.2 H8S/2426, H8S/2426R, H8S/2424 Group SS Control Register L (SSCRL) SSCRL selects operating mode, software reset, and transmit/receive data length. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 R/W Reserved This bit is always read as 0. The write value should always be 0. 6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock synchronous mode.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.3.3 Section 19 Synchronous Serial Communication Unit (SSU) SS Mode Register (SSMR) SSMR selects the MSB first/LSB first, clock polarity, clock phase, and clock rate of synchronous serial communication. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB First/LSB First Select Selects that the serial data is transmitted in MSB first or LSB first. 0: LSB first 1: MSB first 6 CPOS 0 R/W Clock Polarity Select Selects the SSCK clock polarity.
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Section 19 Synchronous Serial Communication Unit (SSU) 19.3.4 H8S/2426, H8S/2426R, H8S/2424 Group SS Enable Register (SSER) SSER performs transfer/receive control of synchronous serial communication and setting of interrupt enable. Bit Bit Name Initial Value R/W Description 7 TE 0 R/W Transmit Enable 6 RE 0 R/W Receive Enable When this bit is set to 1, transmission is enabled. When this bit is set to 1, reception is enabled. 5, 4 ⎯ All 0 R/W Reserved These bits are always read as 0.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.3.5 Section 19 Synchronous Serial Communication Unit (SSU) SS Status Register (SSSR) SSSR is a status flag register for interrupts. Bit Bit Name Initial Value R/W Description 7 ⎯ 0 ⎯ 6 ORER 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Overrun Error If the next data is received while RDRF = 1, an overrun error occurs, indicating abnormal termination.
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Section 19 Synchronous Serial Communication Unit (SSU) H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value R/W Description 2 TDRE 1 R/W 1 RDRF 0 R/W 0 CE 0 R/W Transmit Data Empty Indicates whether or not SSTDR contains transmit data. [Setting conditions] • When the TE bit in SSER is 0 • When data is transferred from SSTDR to SSTRSR and SSTDR is ready to be written to.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.3.6 Section 19 Synchronous Serial Communication Unit (SSU) SS Control Register 2 (SSCR2) SSCR2 is a register that enables/disables the open-drain outputs of the SSO, SSI, SSCK, and SCS pins, selects the assert timing of the SCS pin, data output timing of the SSO pin, and set timing of the TEND bit.
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Section 19 Synchronous Serial Communication Unit (SSU) H8S/2426, H8S/2426R, H8S/2424 Group Bit Bit Name Initial Value R/W Description 3 SCSATS 0 R/W Selects the assertion timing of the SCS pin (valid in SSU and master mode). 0: Min. values of tLEAD and tLAG are 1/2 × tSUcyc 1: Min.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.3.7 Section 19 Synchronous Serial Communication Unit (SSU) SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3) SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0 and SSTDR1 are valid. When 24-bit data length is selected, SSTDR0, SSTDR1, and SSTDR2 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid.
PAGE 1080
H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) 19.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3) SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0 and SSRDR1 are valid. When 24-bit data length is selected, SSRDR0, SSRDR1, and SSRDR2 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.4 Operation 19.4.1 Transfer Clock Section 19 Synchronous Serial Communication Unit (SSU) A transfer clock can be selected from eight internal clocks and an external clock. When using this module, set the SCKS bit in SSCRH to 1 to select the SSCK pin as a serial clock. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is used as an output pin.
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Section 19 Synchronous Serial Communication Unit (SSU) 19.4.3 H8S/2426, H8S/2426R, H8S/2424 Group Relationship between Data Input/Output Pins and Shift Register The connection between data input/output pins and the SS shift register (SSTRSR) depends on the combination of the MSS and BIDE bits in SSCRH and the SSUMS bit in SSCRL. Figure 19.3 shows the relationship.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.4.4 Section 19 Synchronous Serial Communication Unit (SSU) Communication Modes and Pin Functions The SSU switches the input/output pin (SSI, SSO, SSCK, and SCS) functions according to the communication modes and register settings. When a pin is used as an input pin, clear the corresponding bit in each data direction register (DDR) to 0. The relationship of communication modes and input/output pin functions are shown in tables 19.4 to 19.6. Table 19.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Table 19.5 Communication Modes and Pin States of SSCK Pin Communication Mode SSU communication mode Register Setting Pin State SSUMS MSS SCKS SSCK 0 0 0 ⎯ 1 Input 0 ⎯ 1 Output 0 ⎯ 1 Input 0 ⎯ 1 Output 1 Clock synchronous 1 communication mode 0 1 [Legend] ⎯: Not used as SSU pin Table 19.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.4.5 Section 19 Synchronous Serial Communication Unit (SSU) SSU Mode In SSU mode, data communications are performed via four lines: clock line (SSCK), data input line (SSI or SSO), data output line (SSI or SSO), and chip select line (SCS). In addition, the SSU supports bidirectional mode in which a single pin functions as data input and data output lines. (1) Initial Settings in SSU Mode Figure 19.4 shows an example of the initial settings in SSU mode.
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Section 19 Synchronous Serial Communication Unit (SSU) (2) H8S/2426, H8S/2426R, H8S/2424 Group Data Transmission Figure 19.5 shows an example of transmission operation, and figure 19.6 shows a flowchart example of data transmission. When transmitting data, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) 1 frame SCS 1 frame SSCK SSO Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 7 SSTDR0 (LSB first transmission) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR0 (MSB first transmission) TDRE TEND LSI operation User operation TXI interrupt generated TEI interrupt generated TXI interrupt generated TEI interrupt generated Data written to SSTDR0 Data written to SSTDR0 Figure 19.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) 1 frame SCS SSCK SSO (LSB first) Bit 0 Bit 1 SSO (MSB first) Bit 7 Bit 6 Bit 6 to Bit 7 Bit 0 Bit 1 Bit 0 Bit 7 Bit 6 SSTDR2 Bit 1 to to Bit 6 Bit 7 Bit 0 Bit 1 Bit 0 Bit 7 Bit 6 SSTDR1 SSTDR0 to to Bit 6 Bit 7 Bit 1 Bit 0 SSTDR0 Bit 1 SSTDR1 to SSTDR2 TDRE TEND TXI interrupt generated LSI operation User operation TEI interrupt generated Data written to SSTDR0, SSTDR1, and S
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR TDRE = 1? [1] Initial setting: Specify the transmit data format. No [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) (3) Data Reception Figure 19.7 shows an example of reception operation, and figure 19.8 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit to 1 and dummy-reading SSRDR, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) 1 frame SCS SSCK SSI (LSB first) Bit 0 Bit 1 Bit 2 SSI (MSB first) Bit 7 Bit 6 Bit 5 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 0 Bit 1 Bit 2 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 3 SSRDR1 Bit 4 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 2 Bit 1 Bit 0 SSRDR0 SSRDR0 Bit 4 Bit 3 SSRDR1 RDRF RXI interrupt generated LSI operation User operation Dummy-read SSRDR0 and SSRDR1 Figure 19.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) 1 frame SCS SSCK SSI (LSB first) Bit 0 SSI (MSB first) Bit 7 to Bit 7 SSRDR3 to Bit 0 SSRDR0 Bit 0 to Bit 7 Bit 0 SSRDR2 Bit 7 to Bit 0 to Bit 7 SSRDR1 Bit 7 SSRDR1 to Bit 0 SSRDR2 Bit 0 to Bit 7 SSRDR0 Bit 7 to Bit 0 SSRDR3 RDRF LSI operation User operation RXI interrupt generated Dummy-read SSRDR0, SSRDR1, SSRDR2 and SSRDR3 Figure 19.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Dummy-read SSRDR [1] Initial setting: Specify the receive data format. [2] Start reception: When SSRDR is dummy-read with RE = 1, reception is started. Read SSSR No RDRF = 1? Yes ORER = 1? Yes No [4] Consecutive data reception? Yes [3] [3], [6] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR.
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Section 19 Synchronous Serial Communication Unit (SSU) (4) H8S/2426, H8S/2426R, H8S/2424 Group Data Transmission/Reception Figure 19.9 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR [1] Initial setting: Specify the transmit/receive data format. No TDRE = 1? Yes Write transmit data to SSTDR [3] Check the SSU state: Read SSSR confirming that the RDRF bit is 1. A change of the RDRF bit (from 0 to 1) can be notified by RXI interrupt.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) SCS Pin Control and Conflict Error 19.4.6 When bits CSS1 and CSS0 in SSCRH are specified to B'10 and the SSUMS bit in SSCRL is cleared to 0, the SCS pin functions as an input (Hi-Z) to detect conflict error. The conflict detection period is from setting the MSS bit in SSCRH to 1 to starting serial transfer and after transfer ends.
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H8S/2426, H8S/2426R, H8S/2424 Group 19.4.7 Section 19 Synchronous Serial Communication Unit (SSU) Clock Synchronous Communication Mode In clock synchronous communication mode, data communications are performed via three lines: clock line (SSCK), data input line (SSI), and data output line (SSO). (1) Initial Settings in Clock Synchronous Communication Mode Figure 19.12 shows an example of the initial settings in clock synchronous communication mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) (2) Data Transmission Figure 19.13 shows an example of transmission operation, and figure 19.14 shows a flowchart example of data transmission. When transmitting data in clock synchronous communication mode, the SSU operates as shown below. In master mode, the SSU outputs a transfer clock and data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR TDRE = 1? [4][1] Initial setting: Specify the transmit data format. No [3] Procedure for consecutive data transmission: To continue data transmission, confirm that the TDRE bit is 1 meaning that SSTDR is ready to be written to. After that, data can be written to SSTDR. The TDRE bit is automatically cleared to 0 by writing data to SSTDR.
PAGE 1100
H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) (3) Data Reception Figure 19.15 shows an example of reception operation, and figure 19.16 shows a flowchart example of data reception. When receiving data, the SSU operates as shown below. After setting the RE bit in SSER to 1, the SSU starts data reception. In master mode, the SSU outputs a transfer clock and receives data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) [1] Start [1] [2], [4] Receive error processing: When a receive error occurs, execute the designated error processing after reading the ORER bit in SSSR. After that, clear the ORER bit to 0. While the ORER bit is set to 1, transmission or reception is not resumed. Initial setting Read SSSR No RDRF = 1? Yes ORER = 1? Initial setting: Specify the receive data format.
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Section 19 Synchronous Serial Communication Unit (SSU) (4) H8S/2426, H8S/2426R, H8S/2424 Group Data Transmission/Reception Figure 19.17 shows a flowchart example of simultaneous transmission/reception. The data transmission/reception is performed combining the data transmission and data reception as mentioned above. The data transmission/reception is started by writing transmit data to SSTDR with TE = RE = 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) Start [1] Initial setting [2] Read TDRE in SSSR [1] Initial setting: Specify the transmit/receive data format. No TDRE = 1? Yes Write transmit data to SSTDR [2] Check the SSU state and write transmit data: Write transmit data to SSTDR after reading and confirming that the TDRE bit in SSSR is 1. The TDRE bit is automatically cleared to 0 and transmission is started by writing data to SSTDR.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 19 Synchronous Serial Communication Unit (SSU) 19.5 Interrupt Requests The SSU interrupt requests are an overrun error, a conflict error, a receive data register full, transmit data register empty, and a transmit end interrupts.
PAGE 1105
H8S/2426, H8S/2426R, H8S/2424 Group Section 20 RAM Section 20 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), see section 3.2.2, System Control Register (SYSCR).
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Section 20 RAM Page 1076 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Section 21 Flash Memory The flash memory in this LSI can be accessed in three programming modes: user programming mode, boot mode, and programmer mode. Table 21.1 gives an overview of the flash memory specifications (refer to section 1, Overview, for items that are not shown in table 21.1). Table 21.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Table 21.2 Overview of Flash Memory Programming Modes On-board Programming Mode Item Functional overview Off-board Mode User Programming Mode Boot Mode The user ROM is programmed by the CPU through execution of software commands. The user ROM is programmed The user ROM is through the on-chip SCI programmed through a interface. dedicated parallel programmer.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.1 Section 21 Flash Memory Memory Map This ROM is divided into the user ROM and the data flash. Figure 21.1 shows a block diagram of the flash memory. The user ROM and data flash are divided into multiple blocks. The user ROM can be programmed in user programming mode, boot mode, or programmer mode.
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Section 21 Flash Memory 21.2 H8S/2426, H8S/2426R, H8S/2424 Group Register Descriptions The flash memory has the following registers. • Flash memory control register 1 (FLMCR1) • Flash memory data block protect register (FLMDBPR) • Flash memory status register (FLMSTR) Note: When the FLSHE bit in SYSCR is 0, the read values are undefined and registers cannot be modified. Page 1080 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.2.1 Flash Memory Control Register 1 (FLMCR1) Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved The initial value should not be changed. 6 CBIDB 1 R/W CPU Programming Mode Select Setting this bit to 0 (CPU programming mode) enables command acceptance. 0: CPU programming mode enabled 1: CPU programming mode disabled 5 ⎯ 0 ⎯ Reserved The initial value should not be changed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.2.2 Flash Memory Data Block Protect Register (FLMDBPR) Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved The initial value should not be changed. ⎯ 6 0 ⎯ Reserved The initial value should not be changed. 5 ⎯ 0 ⎯ 4 ⎯ 0 ⎯ Reserved The initial value should not be changed. Reserved The initial value should not be changed. ⎯ 3 0 ⎯ Reserved The initial value should not be changed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.2.3 Flash Memory Status Register (FLMSTR) Bit Bit Name Initial Value R/W 7 ⎯ 0 ⎯ Description Reserved The initial value should not be changed. ⎯ 6 0 ⎯ Reserved The initial value should not be changed. 5 FMERSF* 0 R Erase or Blank Check Status Flag 0: Successfully completed 1: Ended with an error ⎯ 4 0 ⎯ Reserved The initial value should not be set.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.3 On-Board Programming Mode When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has two operating modes: SCI boot mode and user programming mode. Table 21.3 shows the pin setting for each operating mode. Table 21.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.3.1 Section 21 Flash Memory User Programming Mode In the user programming mode, the flash memory can be programmed by the CPU through execution of software commands. In this mode, the user ROM and data flash can be programmed without using a ROM programmer with the microcomputer mounted on a system board. The programming and block erase commands should be executed only in each block area of the user ROM and data flash.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.3.2 EW0 Mode Setting the FMCMDEN bit in FLMCR1 to 1 shifts the flash memory into the user programming mode, in which commands can be accepted. Figure 21.2 shows how to set and clear the EW0 mode. Programming and erasure are controlled through software commands. The flash memory state after programming or erasure can be checked through FLMSTR or the status register.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.4 Section 21 Flash Memory Software Commands The following describes the software commands. A command or data should be read or written in 16-bit units at an even address in the user ROM or data flash area. When a command code is written, the lower eight bits (D7 to D0) are ignored. Table 21.
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Section 21 Flash Memory 21.4.1 H8S/2426, H8S/2426R, H8S/2424 Group Read Array This command reads the flash memory. Write H'FFxx in the first bus cycle to shift the flash memory into the read array mode. Specify the target read address in the next bus cycle after setting the CBIDB bit in FLMCR1 to 1, and data is read from the address in 16-bit units. As the flash memory stays in the read array mode until another command is issued, multiple addresses can be read in sequence. 21.4.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.4.4 Section 21 Flash Memory Program This command writes data to the flash memory in 2-word units. Write H'41xx in the first bus cycle and write data to the target address in the second and third bus cycles; the flash memory starts automatic writing (programming and verifying data). The address value specified in the first bus cycle should be the same even address as that specified in the second bus cycle.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Start Write command code "H'41xx" to the target write address. Write data to the target write address. FMRDY = 1? NO YES Full status check End of programming Note: Write the command code and data to even addresses. Figure 21.3 Flowchart of Program Command Processing Page 1090 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.4.5 Section 21 Flash Memory Block Erase Write H'20xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the target block in the second cycle; automatic erasure (erasing data and verifying the erased status) starts in the specified block. Completion of automatic erasure can be checked through the FMRDY bit in FLMSTR. The FMRDY bit is 0 (busy) during automatic erasure and becomes 1 (ready) when erasure is completed.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Start Write command code "H'20xx"*1 Write H'D0xx to the lowest address of the block. NO FMRDY = 1? YES Full status check *2*3 End of block erase Notes:1. Write the command code and data to even addresses. 2. See figure 21.6. 3. If an erase error occurs, repeat a sequence of the clear status register command -> block erase command at least three times until no erase error occurs. Figure 21.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.4.6 Section 21 Flash Memory Block Blank Check This command checks if a block is blank (the erased state). Write H'25xx in the first bus cycle and H'D0xx to the lowest address (an even address) of the target block in the second cycle; the check result will be stored in the FMERSF bit in FLMSTR. After the FMRDY bit in FLMSTR has become 1 (ready), read the FMERSF bit. Figure 21.5 shows a flowchart of the block blank check command processing.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.5 Status Register The status register indicates the state of flash memory operation and whether erasure or programming has ended successfully or with an error. The status register contents can be read through the FMRDY, FMPRSF, and FMERSF bits in FLMSTR. Table 21.6 shows the status register. In the EW0 mode, the status register can be read with the following timing.
PAGE 1125
H8S/2426, H8S/2426R, H8S/2424 Group 21.5.1 Section 21 Flash Memory Sequencer Status (FMRDY Bit) The sequencer status bit indicates the state of flash memory operation. Its value is 0 during execution of a program, block erase, or block blank check and 1 in other cases. 21.5.2 Erase Status (FMERSF Bit) Refer to section 21.6, Full Status Check. 21.5.3 Programming Status (FMPRSF Bit) Refer to section 21.6, Full Status Check. R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory 21.6 Full Status Check When an error occurs, the FMERSF or FMPRSF bit in FLMSTR becomes 1 to indicate occurrence of the error. Read these status bits (full status check) to check the operation results. Table 21.7 shows the errors and FLMSTR status and figure 21.6 shows a flowchart of full status check processing and corrective actions for each error. Table 21.
PAGE 1127
H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Full status check FMPRSF = 1 and FMERSF =1 ? YES Command sequence error . . . (1) Execute a clear status register command to clear the FMPRSF and FMERSF bits to 0 (successfully completed state). (2) Check if the command was input correctly, and execute it again. NO FMERSF = 0? NO Erase error . . . (1) Execute a clear stats register command to clear the FMERSF bit to 0 (successfully completed state). (2) Execute a block erase command.
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Section 21 Flash Memory 21.7 Notes on User Programming Mode 21.7.1 Prohibited Interrupts (EW0 Mode) H8S/2426, H8S/2426R, H8S/2424 Group The NMI and watchdog timer interrupts can be used because FLMCR1 is forcibly initialized when an interrupt is generated; specify the destination address of each interrupt routine in the fixed vector table. Flash memory programming is terminated when an NMI interrupt or a watchdog timer interrupt occurs.
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H8S/2426, H8S/2426R, H8S/2424 Group 21.8 Section 21 Flash Memory Boot Mode Setting the mode pins to mode 3 and resetting the hardware shifts the flash memory into boot mode. In this mode, the embedded standard program is executed. 21.9 SCI Boot Mode SCI boot mode executes programming/erasing of the user ROM by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_1.
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Section 21 Flash Memory 21.10 H8S/2426, H8S/2426R, H8S/2424 Group Serial Communication Interface Specification for Boot Mode Initiating boot mode enables the boot program to communicate with the host by using the on-chip SCI_I. The serial communication interface specification is shown below. (1) Status The boot program has three states. 1. Bit-Rate-Adjustment State In this state, the boot program adjusts the bit rate to communicate with the host.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory These boot program states are shown in figure 21.8. Reset Bit-rate-adjustment state Inquiry/response wait Response Inquiry Operations for inquiry and selection Transition to programming/erasing Operations for response Operations for erasing user MATs Programming/erasing wait Programming Erasing Operations for programming Operations for erasing Checking Operations for checking Figure 21.8 Boot Program States R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (2) Bit-Rate-Adjustment State The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 21.9.
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H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 21 Flash Memory Communications Protocol After adjustment of the bit rate, the protocol for communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These commands and responses are comprised of a single byte. These are consists of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory One-byte command or one-byte response Command or response n-byte Command or n-byte response Data Size Checksum Command or response Error response Error code Error response 128-byte programming Address Data (n bytes) Command Memory read response Size Checksum Data Response Checksum Figure 21.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 21 Flash Memory Inquiry/Selection State The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Inquiry and selection commands are listed below. Table 21.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition command (H'40). The host can choose the needed commands out of the commands and inquiries listed above. The boot program status inquiry command (H'4F) is valid even after the boot program has received the programming/erasing transition command (H'40).
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H8S/2426, H8S/2426R, H8S/2424 Group (b) Section 21 Flash Memory Device Selection The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made. Command H'10 Size Device code SUM • Command, H'10, (1 byte): Device selection • Size (1 byte): Amount of device-code data This is fixed at 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (d) Clock Mode Selection The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands. Command H'11 Size Mode SUM • Command, H'11, (1 byte): Selection of clock mode • Size (1 byte): Amount of data that represents the modes This is fixed at 1.
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H8S/2426, H8S/2426R, H8S/2424 Group (e) Section 21 Flash Memory Multiplication Ratio Inquiry The boot program will return the supported multiplication and division ratios.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (f) Operating Clock Frequency Inquiry The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
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H8S/2426, H8S/2426R, H8S/2424 Group (g) Section 21 Flash Memory User ROM Information Inquiry The boot program will return the number of user ROMs and their addresses.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (h) Erased Block Information Inquiry The boot program will return the number of erased blocks and their addresses.
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H8S/2426, H8S/2426R, H8S/2424 Group (j) Section 21 Flash Memory New Bit-Rate Selection The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory • SUM (1 byte): Checksum Response H'06 • Response, H'06, (1 byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK. Error response H'BF ERROR • Error response, H'BF, (1 byte): Error response to selection of new bit rate • ERROR: (1 byte): Error code H'11: Sum check error H'24: Bit-rate selection disable error The rate is not available.
PAGE 1145
H8S/2426, H8S/2426R, H8S/2424 Group (5) Section 21 Flash Memory Received Data Check The methods for checking of received data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Confirmation H'06 • Confirmation, H'06, (1 byte): Confirmation of a new bit rate Response H'06 • Response, H'06, (1 byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 21.11.
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H8S/2426, H8S/2426R, H8S/2424 Group (6) Section 21 Flash Memory Transition to Programming/Erasing State The boot program will transfer the erasing program, and erase the user ROMs. On completion of this erasure, ACK will be returned and the programming/erasing state will be entered. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state.
PAGE 1148
Section 21 Flash Memory (8) H8S/2426, H8S/2426R, H8S/2424 Group Command Order The order for commands in the inquiry/selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4.
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H8S/2426, H8S/2426R, H8S/2424 Group (9) Section 21 Flash Memory Programming/Erasing State A programming selection command makes the boot program select the programming method, an 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. The programming/ erasing commands are listed below. Table 21.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory Where the sequence of programming operations that is executed includes programming with another method or of another ROM, the procedure must be repeated from the programming selection command. The sequence for programming-selection and 128-byte programming commands is shown in figure 21.12.
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H8S/2426, H8S/2426R, H8S/2424 Group (b) Section 21 Flash Memory 128-Byte Programming The boot program will use the programming program transferred by the programming selection to program the user ROMs in response to 128-byte programming. Command H'50 Address Data ··· ··· SUM • Command, H'50, (1 byte): 128-byte programming • Programming address (4 bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (c) Programming End Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing. Command H'50 Address SUM • Command, H'50, (1 byte): 128-byte programming • Programming address (4 bytes): End code is H'FF, H'FF, H'FF, H'FF.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (10) Erasure Erasure is performed with the erasure selection and block erasure command. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block-erasure command from the host with the block number H'FF will stop the erasure operating.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (a) Erasure Selection The boot program will transfer the erasure program. User ROM data is erased by the transferred erasure program. Command H'48 • Command, H'48, (1 byte): Erasure selection Response H'06 • Response, H'06, (1 byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (11) Memory Read The boot program will return the data stored in the specified address in response to a memory read command. Command H'52 Size Area Read size Read address SUM • Command, H'52, (1 byte): Memory read • Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) • Area (1 byte): H'01: User ROM area An address error occurs when the area setting is incorrect.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (12) User ROM Sum Check The boot program will add all the data bytes in the user ROM area and return the result in response to a user ROM sum check command. Command H'4B • Command, H'4B, (1 byte): Sum check for user ROM Response H'5B Size Checksum of user ROM SUM • Response, H'5B, (1 byte): Response to the user ROM sum check • Size (1 byte): The number of bytes that represents the checksum This is fixed to 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (14) User ROM Blank Check The boot program will check to see if the whole user ROM area is blank and return the result in response to a user ROM blank check command. Command H'4D • Command, H'4D, (1 byte): Blank check for user ROM Response H'06 • Response, H'06, (1 byte): Response to the user ROM blank check If all user ROM areas are blank (H'FF), the boot program will return ACK.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory (16) Boot Program Status Inquiry The boot program will return indications of its present state and error condition in response to a boot program status inquiry command. This inquiry can be made in the inquiry/selection state or the programming/erasing state.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 21 Flash Memory • ERROR (1 byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred. Table 21.
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Section 21 Flash Memory 21.11 H8S/2426, H8S/2426R, H8S/2424 Group Programmer Mode Along with the on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In the programmer mode, a generalpurpose PROM programmer can be used to freely write programs to the on-chip ROM. Program/erase is possible on the user ROM. The PROM programmer must support Renesas microcomputers with 256-Kbyte flash memory as a device type.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator Section 22 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and internal clocks. The clock pulse generator consists of an oscillator circuit, a system-clock PLL circuit and a divider. Figure 22.1 shows a block diagram of the clock pulse generator.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator 22.1 Register Descriptions The clock pulse generator has the following registers. • System clock control register (SCKCR) • PLL control register (PLLCR) 22.1.1 System Clock Control Register (SCKCR) SCKCR controls φ clock output and selects operation when the PLLCR register setting is changed. Bit Bit Name Initial Value R/W Description 7 PSTOP 0 R/W φ Clock Output Disable Controls φ output.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator Bit Bit Name Initial Value R/W Description 5 SDPSTP* 0 R/W SDRAMφ Output Disable Controls SDRAMφ. 0: SDRMφ output. 1: Can be used as PH1/CS5/RAS5. When the SDRAMφ output is selected, the pin functions as follows in each power-down mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator 22.1.2 PLL Control Register (PLLCR) PLLCR sets the frequency multiplication factor used by the system-clock PLL circuit. Care must be taken when writing to this register. For details, see section 22.3, System-Clock PLL Circuit and Divider. Bit Bit Name Initial Value R/W Description 7 to 4 ⎯ All 0 ⎯ Reserved These bits are always read as 0 and cannot be modified. 3 ⎯ 0 R/W Reserved This bit can be read from or written to.
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H8S/2426, H8S/2426R, H8S/2424 Group 22.2 Section 22 Clock Pulse Generator Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 22.2.1 Connecting a Crystal Resonator A crystal resonator can be connected as shown in the example in figure 22.2. Select the damping resistance Rd according to table 22.1. When a crystal resonator is used, the range of its frequencies is from 8 to 20 MHz. Figure 22.3 shows the equivalent circuit of the crystal resonator.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator Table 22.2 Crystal Resonator Characteristics Frequency (MHz) 8 12 16 20 RS max (Ω) 80 60 50 40 C0 max (pF) 7 7 7 7 22.2.2 External Clock Input An external clock signal can be input as shown in the examples in figure 22.4. If the XTAL pin is left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is input to the XTAL pin, make sure that the external clock is held high in standby mode.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator Table 22.3 External Clock Input Conditions VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width tEXL 20 ⎯ 20 ⎯ ns Figure 22.5 External clock input high pulse width tEXH 20 ⎯ 20 ⎯ ns External clock rise time tEXr ⎯ 5 ⎯ 5 ns External clock fall time tEXf ⎯ 5 ⎯ 5 ns Clock low pulse width tCL 0.4 0.6 0.4 0.
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Section 22 Clock Pulse Generator 22.3 H8S/2426, H8S/2426R, H8S/2424 Group System-Clock PLL Circuit and Divider The system-clock PLL circuit and divider have the function of multiplying the frequency of the clock from the oscillator by a factor of 1, 2, or dividing by 2. The system clock frequency is set with the STC1 and STC0 bits in PLLCR. The phase of the rising edge of the internal clock is controlled so as to match that of the rising edge of the EXTAL pin.
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H8S/2426, H8S/2426R, H8S/2424 Group 22.4 Usage Notes 22.4.1 Notes on Clock Pulse Generator Section 22 Clock Pulse Generator 1. The following points should be noted since the frequency of φ changes according to the settings of PLLCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of the Electrical Characteristics. In other words, φ must be set to a value between 8 MHz (minimum) and 33 MHz (maximum).
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H8S/2426, H8S/2426R, H8S/2424 Group Section 22 Clock Pulse Generator 22.4.3 Notes on Board Design When using the crystal resonator, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillation circuit to prevent induction from interfering with correct oscillation. See figure 22.6. Prohibited Signal A Signal B This LSI CL2 XTAL EXTAL CL1 Figure 22.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes Section 23 Power-Down Modes In addition to the normal program execution state, this LSI has power-down modes in which operation of the CPU and oscillator is halted and power consumption is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and so on.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes Table 23.
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H8S/2426, H8S/2426R, H8S/2424 Group Notes: 1. 2. 3. 4. 5. 6. Section 23 Power-Down Modes Stopped (Retained) in the table means that internal register values are retained and internal operations are suspended. Stopped (Reset) in the table means that internal register values and internal states are initialized. In module stop function, only modules for which a stop setting has been made are stopped (reset or retained). IRQ8 to IRQ15 are not supported by the H8S/2424 group.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes STBY pin = low Reset state STBY pin = high RES pin = low Hardware standby mode RES pin = high SSBY = 0 SLEEP instruction High-speed mode (Internal clock is PLL circuit output clock) STC1, STC0 ≠ 11 STC1, STC0 = 11 Clock division mode SLEEP instruction MSTPCR = H'FFFF (H'FFFE), EXMSTPCR = H'FFFF, SSBY = 0 Interrupt*1 All module-clocks-stop mode Any interrupt SLEEP instruction External interrupt*2 Program execution state : Transiti
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H8S/2426, H8S/2426R, H8S/2424 Group 23.1 Section 23 Power-Down Modes Register Descriptions The registers relating to the power-down mode are shown below. For details on the PLL control register (PLLCR), see section 22.1.2, PLL Control Register (PLLCR).
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes Bit Bit Name Initial Value R/W Description 5 ⎯ 0 ⎯ Reserved This bit is always read as 0. The initial value should not be changed. 4 ⎯ 0 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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H8S/2426, H8S/2426R, H8S/2424 Group 23.1.2 Section 23 Power-Down Modes Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCR performs module stop state control. Setting a bit to 1, the corresponding module enters the module stop state, while clearing the bit to 0 clears the module stop state.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes • MSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP7 1 R/W A/D converter unit 1 6 MSTP6 1 R/W A/D converter unit 0 5 MSTP5 1 R/W Serial communication interface 4 (SCI_4) 4 MSTP4 1 R/W Serial communication interface 3 (SCI_3) 3 MSTP3 1 R/W Serial communication interface 2 (SCI_2) 2 MSTP2 1 R/W Serial communication interface 1 (SCI_1) 1 MSTP1 1 R/W Serial communication interface 0 (SCI_0) 0 MSTP0 1
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes • EXMSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP23 1 R/W Synchronous serial communication unit (SSU) 6 MSTP22 1 R/W I2C bus interface 2_3 (IIC2_3) 5 MSTP21 1 R/W I2C bus interface 2_2 (IIC2_2) 4 MSTP20 1 R/W I2C bus interface 2_1 (IIC2_1) 3 MSTP19 1 R/W I2C bus interface 2_0 (IIC2_0) 2 MSTP18 1 R/W Reserved This bit can be read or written to. The write value should always be 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes • RMMSTPCRL Bit Bit Name Initial Value R/W Module 7 MSTP39 0 R/W On-chip RAM_7 (H'FEC000 to H'FEDFFF)* 6 MSTP38 0 R/W On-chip RAM_6 (H'FEE000 to H'FEFFFF)* 5 MSTP37 0 R/W On-chip RAM_5 (H'FF0000 to H'FF1FFF) 4 MSTP36 0 R/W On-chip RAM_4 (H'FF2000 to H'FF3FFF) 3 MSTP35 0 R/W On-chip RAM_3 (H'FF4000 to H'FF5FFF) 2 MSTP34 0 R/W On-chip RAM_2 (H'FF6000 to H'FF7FFF) 1 MSTP33 0 R/W On-chip RAM_1 (H'FF8000 to H
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H8S/2426, H8S/2426R, H8S/2424 Group 23.2 Operation 23.2.1 Clock Division Mode Section 23 Power-Down Modes When bits STC1 and STC0 in PLLCR are set to 11, a transition is made to clock division mode, and the system clock frequency is divided with respect to the oscillator frequency. Clock division mode is cancelled by clearing bits STC1 and STC0 to a value other than 11. The timings of transition and clearing depend on the STCS bit setting in SCKCR.
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Section 23 Power-Down Modes 23.2.2 (1) H8S/2426, H8S/2426R, H8S/2424 Group Sleep Mode Transition to Sleep Mode When the SLEEP instruction is executed while the SSBY bit is 0 in SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. (2) Exiting Sleep Mode Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
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H8S/2426, H8S/2426R, H8S/2424 Group 23.2.3 (1) Section 23 Power-Down Modes Software Standby Mode Transition to Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes (3) Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS3 to STS0 in SBYCR should be set as described below. • Using a Crystal Resonator: Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time. Table 23.2 shows the standby times for operating frequencies and settings of bits STS3 to STS0. • Using an External Clock: A PLL circuit stabilization time is necessary.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 23 Power-Down Modes Software Standby Mode Application Example Figure 23.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, after an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), the NMIEG bit is set to 1 (rising edge specification).
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Section 23 Power-Down Modes 23.2.4 (1) H8S/2426, H8S/2426R, H8S/2424 Group Hardware Standby Mode Transition to Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 23 Power-Down Modes Hardware Standby Mode Timing when Power Is Supplied When entering hardware standby mode immediately after the power is supplied, the RES signal must be driven low for a given period with retaining the STBY signal high. After the RES signal is canceled, drive the STBY signal low. (1) Power supply RES (2) Reset period STBY (3) Hardware standby mode Figure 23.4 Hardware Standby Mode Timing when Power Is Supplied 23.2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes Table 23.3 Combinations of SYSCR Settings and Operation in Access to On-Chip RAM Register Settings RAME EXPE mstp Target for Access Description 1 X 1 ⎯ 0 On-chip RAM 1 X External address space 0 X ⎯ 0 23.2.6 This area is not readable/writable and access is prohibited. This area is not readable/writable and access is prohibited.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes φ Clock Output Control 23.3 Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set. Table 23.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 23 Power-Down Modes 23.4 SDRAMφ Clock Output Control Output of the SDRAMφ clock can be controlled by the SDPSTP bit in SCKCR. When the SDPSTP bit is set to 1, the SDRAMφ clock stops at the end of the bus cycle and the pin can be used as a general port. SDRAMφ clock output is enabled when the SDPSTP bit is cleared to 0 regardless of the DDR value. Table 23.5 shows the state of the SDRAMφ pin in each processing state.
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H8S/2426, H8S/2426R, H8S/2424 Group 23.5 Usage Notes 23.5.1 I/O Port Status Section 23 Power-Down Modes In software standby mode, I/O port states are retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. 23.5.2 Current Dissipation during Oscillation Stabilization Standby Period Current dissipation increases during the oscillation stabilization standby period. 23.5.
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Section 23 Power-Down Modes 23.5.6 H8S/2426, H8S/2426R, H8S/2424 Group Notes on Clock Division Mode The following points should be noted in clock division mode. • Select the clock division ratio by the STC1 and STC0 bits so that the frequency of φ is within the operation guaranteed range of clock cycle time tcyc shown in the Electrical Characteristics. In other words, the frequency of φ must be 8 MHz or higher; be careful not so specify φ < 8 MHz. • All the on-chip peripheral modules operate on the φ.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Section 24 List of Registers The address list gives information on the on-chip register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules. The access size is indicated. 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers 24.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Timer start register_1 TSTRB 8 H'FCC0 TPU 16 2 Timer synchronous register_1 TSYRB 8 H'FCC1 TPU 16 2 Timer control register_6 TCR_6 8 H'FCD0 TPU_6 16 2 Timer mode register_6 TMDR_6 8 H'FCD1 TPU_6 16 2 Timer I/O control register H_6 TIORH_6 8 H'FCD2 TPU_6 16 2 Timer I/O control register L_6 TIORL_6 8 H'FCD3 TPU_6 16
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H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Timer I/O control register L_9 TIORL_9 8 H'FD03 TPU_9 16 2 Timer interrupt enable register_9 TIER_9 8 H'FD04 TPU_9 16 2 Timer status register_9 TSR_9 8 H'FD05 TPU_9 16 2 Timer counter_9 TCNT_9 16 H'FD06 TPU_9 16 2 Timer general register A_9 TGRA_9 16 H'FD08 TPU_9 16 2 Timer general register B_9 TGRB_9 16 H'FD0A TPU_9
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H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Port E open drain control register PEODR 8 H'FD48 PORT 8 2 Port F open drain control register PFODR 8 H'FD49 PORT 8 2 Port G open drain control register PGODR 8 H'FD4A PORT 8 2 Port H open drain control register PHODR 8 H'FD4B PORT 8 2 Port J open drain control register PJODR 8 H'FD4C PORT 8 2 2 ICCRA_0 8 H'FD58 IIC2
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H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Abbreviation Number of Bits Address Module Data Width Access States 2 ICIER_3 8 H'FD73 IIC2_3 8 2 2 I C bus status register_3 ICSR_3 8 H'FD74 IIC2_3 8 2 Slave address register_3 SAR_3 8 H'FD75 IIC2_3 8 2 ICDRT_3 8 H'FD76 IIC2_3 8 2 Register Name I C bus interrupt enable register_3 2 I C transfer data register_3 2 I C receive data register_3 ICDRR_3 8 H'FD77 IIC2_3 8 2 Serial expansion mode register_
PAGE 1199
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address EXDMA destination address register_3 EDDAR_3 32 H'FDF4 EXDMAC_ 16 3 3* 2 EXDMA transfer count register_3 EDTCR_3 32 H'FDF8 EXDMAC_ 16 3 3* 2 EXDMA mode control register_3 EDMDR_3 16 H'FDFC EXDMAC_ 16 3 3* 2 EXDMA address control register_3 EDACR_3 16 H'FDFE EXDMAC_ 16 3 3* 2 Interrupt priority register A IPRA 16 H'FE00 INT 16 2 Interrupt priority register B
PAGE 1200
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Port A data direction register PADDR 8 H'FE29 PORT 8 2 Port B data direction register PBDDR 8 H'FE2A PORT 8 2 Port C data direction register PCDDR 8 H'FE2B PORT 8 2 Port D data direction register PDDDR 8 H'FE2C PORT 8 2 Port E data direction register PEDDR 8 H'FE2D PORT 8 2 Port F data direction register PFDDR 8 H'FE2
PAGE 1201
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Timer control register_3 TCR_3 8 H'FE80 TPU_3 16 2 Timer mode register_3 TMDR_3 8 H'FE81 TPU_3 16 2 Timer I/O control register H_3 TIORH_3 8 H'FE82 TPU_3 16 2 Timer I/O control register L_3 TIORL_3 8 H'FE83 TPU_3 16 2 Timer interrupt enable register_3 TIER_3 8 H'FE84 TPU_3 16 2 Timer status register_3 TSR_3 8 H'FE85
PAGE 1202
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Bus width control register ABWCR 8 H'FEC0 BSC 16 2 Access state control register ASTCR 8 H'FEC1 BSC 16 2 Wait control register AH WTCRAH 8 H'FEC2 BSC 16 2 Wait control register AL WTCRAL 8 H'FEC3 BSC 16 2 Wait control register BH WTCRBH 8 H'FEC4 BSC 16 2 Wait control register BL WTCRBL 8 H'FEC5 BSC 16 2 Read strob
PAGE 1203
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Memory address register_1AH MAR_1AH 16 H'FEF0 DMAC 16 2 Memory address register_1AL MAR_1AL 16 H'FEF2 DMAC 16 2 I/O address register_1A IOAR_1A 16 H'FEF4 DMAC 16 2 Transfer count register_1A ETCR_1A 16 H'FEF6 DMAC 16 2 Memory address register_1BH MAR_1BH 16 H'FEF8 DMAC 16 2 Memory address register_1BL MAR_1BL 16 H'FEF
PAGE 1204
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Standby control register SBYCR 8 H'FF3A SYSTEM 8 2 System clock control register SCKCR 8 H'FF3B SYSTEM 8 2 System control register SYSCR 8 H'FF3D SYSTEM 8 2 Mode control register MDCR 8 H'FF3E SYSTEM 8 2 Module stop control register H MSTPCRH 8 H'FF40 SYSTEM 8 2 Module stop control register L MSTPCRL 8 H'FF41 SYSTEM
PAGE 1205
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Port A register PORTA 8 H'FF59 PORT 8 2 Port B register PORTB 8 H'FF5A PORT 8 2 Port C register PORTC 8 H'FF5B PORT 8 2 Port D register PORTD 8 H'FF5C PORT 8 2 Port E register PORTE 8 H'FF5D PORT 8 2 Port F register PORTF 8 H'FF5E PORT 8 2 Port G register PORTG 8 H'FF5F PORT 8 2 Port 1 data register P1DR
PAGE 1206
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Serial mode register_0 SMR_0 8 H'FF78 SCI_0 8 2 Bit rate register_0 BRR_0 8 H'FF79 SCI_0 8 2 Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2 Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2 Serial status register_0 SSR_0 8 H'FF7C SCI_0 8 2 Receive data register_0 RDR_0 8 H'FF7D SCI_0 8 2 Smart card mode regist
PAGE 1207
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States D/A data register 2 DADR2 8 H'FFA8 D/A 8 2 D/A data register 3 DADR3 8 H'FFA9 D/A 8 2 D/A control register 23 DACR23 8 H'FFAA D/A 8 2 Timer control register_0 TCR_0 8 H'FFB0 TMR_0 16 2 Timer control register_1 TCR_1 8 H'FFB1 TMR_1 16 2 Timer control/status register_0 TCSR_0 8 H'FFB2 TMR_0 16 2 Timer control/status
PAGE 1208
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Name Abbreviation Number of Bits Address Module Data Width Access States Timer mode register_0 TMDR_0 8 H'FFD1 TPU_0 16 2 Timer I/O control register H_0 TIORH_0 8 H'FFD2 TPU_0 16 2 Timer I/O control register L_0 TIORL_0 8 H'FFD3 TPU_0 16 2 Timer interrupt enable register_0 TIER_0 8 H'FFD4 TPU_0 16 2 Timer status register_0 TSR_0 8 H'FFD5 TPU_0 16 2 Timer counter_0 TCNT_0 16 H'FFD6 TPU_0
PAGE 1209
H8S/2426, H8S/2426R, H8S/2424 Group 24.2 Section 24 List of Registers Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
PAGE 1210
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D_1 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD
PAGE 1211
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCR_7 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_7 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_7 IOB3 IOB
PAGE 1212
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_9 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_9 TMDR_9 ⎯ ⎯ BFB BFA MD3 MD2 MD1 MD0 TIORH_9 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_9 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 TIER_9 TTGE ⎯ ⎯ TCIEV TGIED TGIEC TGIEB TGIEA TSR_9 ⎯ ⎯ ⎯ TCFV TGFD TGFC TGFB TGFA TCNT_9 Bit 15 Bit 14 Bit 13
PAGE 1213
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TPU_11 TCR_11 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_11 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_11 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_11 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA TSR_11 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TCNT_11 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit
PAGE 1214
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICCRA_1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 IIC2_1 ICCRB_1 BBSY SCP SDAO ⎯ SCLO ⎯ IICRST ⎯ ICMR_1 ⎯ WAIT ⎯ ⎯ BCWP BC2 BC1 BC0 ICIER_1 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT ICSR_1 TDRE TEND RDRF NACKF STOP AL AAS ADZ SAR_1 SVA6 SVA5 SVA4 SVA3 SVA2 SVA1 SVA0 ⎯ ICDRT_1 ICDRT7 ICDRT6 ICDRT5 ICDRT4
PAGE 1215
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module SSTDR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSU SSTDR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSTDR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SSRDR1 Bit 7 Bit 6 Bit 5 Bit 4
PAGE 1216
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 EDDAR_3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 EXDMAC_3*7 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 31 Bit 30 Bit 29 Bit 2
PAGE 1217
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 IPRJ IPRK ITSR SSIER ISCRH ISCRL Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ⎯ IPRJ14 IPRJ13 IPRJ12 ⎯ IPRJ10 IPRJ9 IPRJ8 INT ⎯ IPRJ6 IPRJ5 IPRJ4 ⎯ IPRJ2 IPRJ1 IPRJ0 ⎯ IPRK14 IPRK13 IPRK12 ⎯ IPRK10 IPRK9 IPRK8 ⎯ IPRK6 IPRK5 IPRK4 ⎯ IPRK2 IPRK1 IPRK0 ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 SSI15 SSI14
PAGE 1218
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PAPCR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PORT PBPCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PCPCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PDPCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PEPCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR
PAGE 1219
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 TCNT_3 TGRA_3 TGRB_3 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TPU_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit
PAGE 1220
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module FLASH FLMCR1 ⎯ CBIDB ⎯ ⎯ ⎯ ⎯ ⎯ FMCMDEN FLMDBPR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ FMDBPT0 FLMSTR ⎯ ⎯ FMERSF ⎯ FMPRSF ⎯ ⎯ FMRDY ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 WTCRAH ⎯ W72 W71 W70 ⎯ W62 W61 W60 WTCRAL ⎯ W52 W51 W50 ⎯ W42 W41 W40 WTCRBH ⎯ W32 W31 W30 ⎯
PAGE 1221
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 MAR_0AH MAR_0AL IOAR_0A ETCR_0A MAR_0BH MAR_0BL IOAR_0B ETCR_0B MAR_1AH MAR_1AL IOAR_1A ETCR_1A MAR_1BH MAR_1BL Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DMAC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
PAGE 1222
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DMAC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DMAWER ⎯ ⎯ ⎯ ⎯ WE1B WE1A WE0B WE0A DMATCR ⎯ ⎯ TEE1 TEE0 ⎯ ⎯ ⎯ ⎯ DTID RPE DTDIR DTF3 DTF2 DTF1
PAGE 1223
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module INT INTCR ⎯ ⎯ INTM1 INTM0 NMIEG ⎯ ⎯ ⎯ IER IRQ15E IRQ14E IRQ13E IRQ12E IRQ11E IRQ10E IRQ9E IRQ8E IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F SBYCR SSBY OPE ⎯ ⎯ STS3 STS2 STS1 STS0 SCKCR PSTOP ⎯ S
PAGE 1224
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORT PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PORTD PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PORTE PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTF PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PORTG ⎯ PG6 PG5 PG4 PG3 PG2 PG1 PG0 P1DR P17DR P16DR P15DR
PAGE 1225
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TDRE RDRF ORER FER PER TEND MPB MPBT SCI_0, Smart SSR_0* TDRE RDRF ORER ERS PER TEND MPB MPBT RDR_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ⎯ ⎯ SDIR SINV ⎯ SMIF 4 5 SSR_0* card interface_0 BCP2 ⎯ 4 SMR_1* C/A CHR PE O/E STOP MP CKS1 CKS0 SMR_1*5 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 BRR_1 Bit 7
PAGE 1226
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D_0 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADCSR_0 ADF ADIE ADST ⎯ CH3 CH2 CH1 CH0 ADCR_0 TRGS1 TRGS0 SCANE SC
PAGE 1227
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ⎯ ⎯ ⎯ ⎯ PORT TXD4S RXD4S SCK4S PFCR3 ⎯ PPGS TPUS TMRS PFCR4 WAITS BREQS BACKS BREQOS ⎯ PFCR5 SSO0S1 SSO0S0 SSI0S1 SSI0S0 SSCK0S1 SSCK0S0 SCS0S1 SCS0S0 TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_0 ⎯ ⎯ BFB BFA MD3 MD2 MD1 MD0 TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIORL_0 IOD3 IOD
PAGE 1228
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TPU_2 TCR_2 ⎯ CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TMDR_2 ⎯ ⎯ ⎯ ⎯ MD3 MD2 MD1 MD0 TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 TIER_2 TTGE ⎯ TCIEU TCIEV ⎯ ⎯ TGIEB TGIEA TSR_2 TCFD ⎯ TCFU TCFV ⎯ ⎯ TGFB TGFA TCNT_2 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit
PAGE 1229
H8S/2426, H8S/2426R, H8S/2424 Group 24.
PAGE 1230
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TCR_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_6 TMDR_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIORH_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIORL_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_6 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial
PAGE 1231
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TIORL_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_9 TIER_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCNT_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRA_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRB_9 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial
PAGE 1232
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module PCODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PORT PDODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PEODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PGODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PHODR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P
PAGE 1233
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module ICCRA_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IIC2_3 ICCRB_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ICMR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ICIER_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ICSR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SAR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Init
PAGE 1234
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module EDSAR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EXDMAC_3* EDDAR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EDTCR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EDMDR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EDACR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IPRA Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
PAGE 1235
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module PEDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PORT PFDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PGDDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFCR0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFCR1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PFCR2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P
PAGE 1236
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TIER_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_3 TSR_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCNT_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRA_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRB_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TGRC_3 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initiali
PAGE 1237
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module ABWCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized BSC ASTCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized WTCRAH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized WTCRAL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized WTCRBH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized WTCRBL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized
PAGE 1238
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module ETCR_1A Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMAC MAR_1BH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized MAR_1BL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized IOAR_1B Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized ETCR_1B Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized DMAWER Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Ini
PAGE 1239
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module MSTPCRL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SYSTEM EXMSTPCRH Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized EXMSTPCRL Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PLLCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PCR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PMR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initia
PAGE 1240
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module P3DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PORT P5DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P6DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized P8DR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PADR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PBDR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized PCDR I
PAGE 1241
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module SMR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCI_2 BRR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized SCR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TDR_2 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initialized SSR_2 Initialized ⎯ ⎯ ⎯ Initialized Initialized Initialized Initia
PAGE 1242
H8S/2426, H8S/2426R, H8S/2424 Group Section 24 List of Registers Register High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TCCR_0 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TMR TCCR_1 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCSR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCNT Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized RSTCSR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TSTR Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSYR Initia
PAGE 1243
H8S/2426, H8S/2426R, H8S/2424 Group Register Section 24 List of Registers High- Clock Module All Module Abbreviation Reset Speed Division Sleep Stop Clock Stop Standby Standby Module TCR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TPU_2 TMDR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIOR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TIER_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TSR_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initialized TCNT_2 Initialized ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initializ
PAGE 1244
Section 24 List of Registers Page 1214 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
PAGE 1245
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Section 25 Electrical Characteristics 25.1 Electrical Characteristics for H8S/2426 Group and H8S/2426R Group (3-V Version) 25.1.1 Absolute Maximum Ratings Table 25.1 lists the absolute maximum ratings. Table 25.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V Input voltage (except ports 4, 9, and 2, Vin P32 to P35, P50 and P51, and PJ0 to PJ2) −0.3 to VCC +0.
PAGE 1246
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.1.2 DC Characteristics Table 25.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Typ. Max. Test Unit Conditions ⎯ ⎯ V ⎯ VCC × 0.7 V ⎯ ⎯ V VCC × 0.9 ⎯ VCC +0.3 V RES, NMI, FWE VCC × 0.9 ⎯ VCC +0.3 V EXTAL VCC × 0.7 ⎯ VCC +0.3 V P14 to P17* , P24 to P26*5, 3 port 3* , P50 to P53*3, ports 6*3 and 8*3, 3 ports A to J* 2.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions Output high All output pins voltage VOH VCC − 0.3 ⎯ ⎯ V IOH = −200 μA VCC − 0.5 ⎯ ⎯ V IOH = −1 mA VCC − 0.8 ⎯ ⎯ V IOH = −2 mA ⎯ ⎯ 0.4 V IOL = 4.0 mA ⎯ ⎯ 0.4 V IOL = 8.0 mA ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Ports 4 and 9 ⎯ ⎯ 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.3 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Test Conditions Item Symbol Min. Typ. Max. Unit Three-state Ports 1 to 3, leakage current P50 to P53, (off state) ports 6 and 8, ports A to I | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Input pull-up MOS current −Ip 10 ⎯ 300 μA VCC = 3.0 to 3.
PAGE 1249
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 5.2 (mA) + 1.66 (mA/(MHz)) × f (normal operation) ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode) 5. Applied when RES is low at power-on. Table 25.4 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V* Item Symbol Min. Typ.
PAGE 1250
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.1.3 AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, EXDMAC, and onchip peripheral functions. (1) Clock Timing Table 25.5 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 25.
PAGE 1251
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3V RL C=50pF: Ports A to J (except for PH1 when SDRAMφ is in use.) C=30pF: Ports 1 to 3, P50 to P52, Ports 6 and 8, and PH1 when SDRAMφ∗ is in use. LSI output pin RL=2.4kΩ RH=12kΩ I/O timing test level 1.5V: (Vcc=3.0 to 3.6V) C RH Note: * Not supported by the H8S/2426R Group. Figure 25.1 Output Load Circuit (2) Control Signal Timing Table 25.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (3) Bus Timing Table 25.7 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Max. Test Unit Conditions 20 ns tAS1 0.5 × tcyc −13 ⎯ ns tAS2 1.0 × tcyc −13 ⎯ ns Address setup time 3 tAS3 1.5 × tcyc −13 ⎯ ns Address setup time 4 tAS4 2.0 × tcyc −13 ⎯ ns Address hold time 1 tAH1 0.5 × tcyc −8 ⎯ ns Address hold time 2 tAH2 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Symbol Min. Counter address read data access time 1 tAA1 ⎯ 1.0 × tcyc − 25 ns Counter address read data access time 2 tAA2 ⎯ 1.5 × tcyc − 25 ns Counter address read data access time 3 tAA3 ⎯ 2.0 × tcyc − 25 ns Counter address read data access time 4 tAA4 ⎯ 2.5 × tcyc − 25 ns Counter address read data access time 5 tAA5 ⎯ 3.0 × tcyc − 25 ns Counter address read data access time 6 tAA6 ⎯ 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.8 Bus Timing (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.5 × tcyc −13 ⎯ ns Write data delay time tWDD ⎯ 23 ns Write data setup time 1 tWDS1 0.
PAGE 1255
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Test Conditions Item Symbol Min. Max. Unit OE delay time 1*1 tOED1 ⎯ 15 ns tOED1B ⎯ 19 ns tOED2 ⎯ 15 ns tOED2B ⎯ 19 ns Precharge time 1 tPCH1 1.0 × tcyc −20 ⎯ ns Precharge time 2 tPCH2 1.5 × tcyc −20 ⎯ ns Self-refresh precharge time 1 tRPS1 2.5 × tcyc −20 ⎯ ns Self-refresh precharge time 2 tRPS2 3.
PAGE 1256
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (4) DMAC and EXDMAC Timing Table 25.9 DMAC and EXDMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 25.34 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 ns Figure 25.
PAGE 1257
H8S/2426, H8S/2426R, H8S/2424 Group (5) Section 25 Electrical Characteristics Timing of On-Chip Peripheral Modules Table 25.10 Timing of On-Chip Peripheral Modules Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions 40 ns Figure 25.36 tPWD ⎯ Input data setup time tPRS 25 ⎯ ns Input data hold time tPRH 25 ⎯ ns PPG Pulse output delay time tPOD ⎯ 40 ns Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 25.46 IIC2 SCL input cycle time tSCL 12 tcyc +600 ⎯ ns Figure 25.
PAGE 1259
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item SCS hold time SSU* Master Symbol Min. Max. Unit Test Conditions tLAG 2.5 ⎯ tcyc 2.5 ⎯ Figures 25.48 to 25.51 ⎯ 40 ⎯ 40 Slave Note Master Data output hold time Master tOD Slave tOH Slave −5 ⎯ 0 ⎯ 2.5 ⎯ 2.5 ⎯ ns ns Continuous Master transmit delay time Slave tTD tcyc Slave access time tSA ⎯ 1 tcyc Slave out release time tREL ⎯ 1 tcyc Figures 25.50 and 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.1.5 D/A Conversion Characteristics Table 25.12 D/A Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 8 8 8 Bit Conversion time ⎯ ⎯ 10 μs Absolute accuracy ⎯ ±2.0 ±3.0 LSB 2 MΩ resistive load ⎯ ⎯ ±2.0 LSB 4 MΩ resistive load 25.1.
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H8S/2426, H8S/2426R, H8S/2424 Group Notes: Section 25 Electrical Characteristics 1. When programming is to be performed multiple times on a system, reduce the effective number of programming operations by shifting the writing addresses in sequence and so on until the remaining blank area is as small as possible and only then erasing the entire block once.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.2 Electrical Characteristics for H8S/2424 Group (3-V Version) 25.2.1 Absolute Maximum Ratings Table 25.14 lists the absolute maximum ratings. Table 25.14 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +4.3 V Input voltage (except ports 4, 9, and 2, Vin P32 to P35, P50 and P51, and P81 and P83) −0.3 to VCC +0.
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H8S/2426, H8S/2426R, H8S/2424 Group 25.2.2 Section 25 Electrical Characteristics DC Characteristics Table 25.15 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Typ. Max. Test Unit Conditions ⎯ ⎯ V ⎯ VCC × 0.7 V ⎯ ⎯ V VCC × 0.9 ⎯ VCC +0.3 V VCC × 0.7 ⎯ VCC +0.3 V P10 to P11* , P14 to P17*5, 5 P24 to P26* , 3 port 3* , P50 to P53*3, 3 port 8* , ports A 3 to G* 2.2 ⎯ VCC +0.3 V Ports 4 and 9 2.2 ⎯ AVCC +0.
PAGE 1264
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions Output high All output pins voltage VOH VCC − 0.3 ⎯ ⎯ V IOH = −200 μA VCC − 0.5 ⎯ ⎯ V IOH = −1 mA VCC − 0.8 ⎯ ⎯ V IOH = −2 mA ⎯ ⎯ 0.4 V IOL = 4.0 mA ⎯ ⎯ 0.4 V IOL = 8.0 mA ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Port 4, Port 9 ⎯ ⎯ 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.16 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1 Item Symbol Min. Typ. Max. Unit Test Conditions Three-state leakage current (off state) Ports 1 to 3, P50 to P53, port 8, ports A to G | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Input pull-up MOS current Ports A to E −Ip 10 ⎯ 300 μA VCC = 3.0 to 3.
PAGE 1266
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 5.2 (mA) + 1.66 (mA/(MHz)) × f (normal operation) ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode) 5. Applied when RES is low at power-on. Table 25.17 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V* Item Symbol Min. Typ.
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H8S/2426, H8S/2426R, H8S/2424 Group 25.2.3 Section 25 Electrical Characteristics AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, and on-chip peripheral functions. (1) Clock Timing Table 25.18 Clock Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3V RL C=50pF: Ports A to G C=30pF: Ports 1 to 3, P50 to P53, and Port8 RL=2.4kΩ RH=12kΩ I/O timing test level1.5V: (Vcc=3.0 to 3.6V) LSI output pin C RH Figure 25.2 Output Load Circuit (2) Control Signal Timing Table 25.19 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max.
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H8S/2426, H8S/2426R, H8S/2424 Group (3) Section 25 Electrical Characteristics Bus Timing Table 25.20 Bus Timing (1) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Address delay time tAD ⎯ 20 ns Address setup time 1 tAS1 0.5 × tcyc −13 ⎯ ns Address setup time 2 tAS2 1.0 × tcyc −13 ⎯ Figures 25.8 to 25.23, 25.34 and 25.35 ns Address setup time 3 tAS3 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions Counter address read data access time 4 tAA4 ⎯ 2.5 × tcyc − 25 ns Counter address read data access time 5 tAA5 ⎯ 3.0 × tcyc − 25 ns Counter address read data access time 6 tAA6 ⎯ 4.0 × tcyc − 25 Figures 25.8 to 25.23, 25.34 and 25.35 ns Multiplexed address delay time tMAD ⎯ 20 ns Multiplexed address setup time 1 tMAS1 0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions CAS delay time 2 tCASD2 ⎯ 15 ns CAS setup time 1 tCSR1 0.5 × tcyc −10 ⎯ ns CAS setup time 2 Figures 25.8 to 25.23, 25.34 and 25.35 tCSR2 1.5 × tcyc −10 ⎯ ns CAS pulse width 1 tCASW1 1.0 × tcyc −20 ⎯ ns CAS pulse width 2 tCASW2 1.5 × tcyc −20 ⎯ ns CAS precharge time 1 tCPW1 1.0 × tcyc −20 ⎯ ns CAS precharge time 2 tCPW2 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (4) DMAC Timing Table 25.21 DMAC Timing Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 25.32 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 Figure 25.31 DACK delay time 1 tDACD1 ⎯ 18 Figures 25.29 and 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Item 8-bit timer Section 25 Electrical Characteristics Symbol Min. Max. Unit Test Conditions tTMOD ⎯ 40 ns Figure 25.40 Timer reset input setup time tTMRS 25 ⎯ ns Figure 25.42 Timer clock input setup time tTMCS 25 ⎯ ns Figure 25.41 Timer clock Single-edge pulse width specification tTMCWH 1.5 ⎯ tcyc Both-edge specification tTMCWL 2.
PAGE 1274
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item SSU* Clock cycle Master Symbol Min. Max. Unit Test Conditions tSUcyc 4 256 tcyc 4 256 Figures 25.48 to 25.51 48 ⎯ 48 ⎯ Slave Clock high pulse width Master Clock low pulse width Master tHI Slave tLO Slave ⎯ ns tRISE ⎯ 12 ns Clock falling time tFALL ⎯ 12 ns tSU 25 ⎯ ns 30 ⎯ 10 ⎯ 10 ⎯ tLEAD 2.5 ⎯ 2.5 ⎯ tLAG 2.5 ⎯ 2.5 ⎯ ⎯ 40 ⎯ 40 −5 ⎯ 0 ⎯ 2.
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H8S/2426, H8S/2426R, H8S/2424 Group 25.2.4 Section 25 Electrical Characteristics A/D Conversion Characteristics Table 25.23 A/D Conversion Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 10 10 10 Bit Conversion time 2.5* ⎯ ⎯ μs Analog input capacitance ⎯ ⎯ 15 pF Permissible signal source impedance ⎯ ⎯ 5 kΩ Nonlinearity error ⎯ ⎯ ±3.
PAGE 1276
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.2.6 Flash Memory Characteristics Table 25.25 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Standard value Item Programming and erase count* 1 Applicable area Min. User ROM 1000* 2 Unit Typ. Max.
PAGE 1277
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.3 Timing Charts (3-V Version) 25.3.1 Clock Timing The clock timings are shown below. tcyc tCH tCf φ tCL tCr Figure 25.3 System Clock Timing tcyc tCH tCf φ tCr tCL tcdif tsdcf tsdcr SDRAMφ tSDCH tSDCL Figure 25.4 SDRAMφ Timing R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 25.5 (1) Oscillation Settling Timing Oscillator φ NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation stabilization time tOSC2 SLEEP instruction Figure 25.5 (2) Oscillation Settling Timing Page 1248 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group 25.3.2 Section 25 Electrical Characteristics Control Signal Timing The control signal timings are shown below. φ tRESS tRESS RES tRESW Figure 25.6 Reset Input Timing φ tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * SSIER setting is necessary to clear software standby mode. Figure 25.7 Interrupt Input Timing R01UH0310EJ0500 Rev. 5.
PAGE 1280
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.3.3 Bus Timing The bus timings are shown below. T2 T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC5 tAA2 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 tAA3 D15 to D0 tAS1 tWRD2 tWRD2 tAH1 HWR, LWR tWDD Write tWSW1 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
PAGE 1281
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T3 T2 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 tAA4 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tRDS2 tAC4 tRDH2 tAA5 D15 to D0 tAS2 tWRD2 tAH1 tWRD1 HWR, LWR tWDS1 tWDD Write tWSW2 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.9 Basic Bus Timing: Three-State Access R01UH0310EJ0500 Rev. 5.
PAGE 1282
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 25.10 Basic Bus Timing: Three-State Access, One Wait Page 1252 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1283
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 Th T2 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tAH1 tASD tASD AS tAS3 tAH3 tRSD1 tRSD1 RD Read (RDNn = 1) tAC5 tRDS1 tRDH1 tRSD1 tRSD2 D15 to D0 tAS3 tAH2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 D15 to D0 tAS3 tWRD2 tWRD2 tAH3 HWR, LWR tWDD Write tWDS2 tWSW1 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
PAGE 1284
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Th T1 T2 T3 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tRSD1 tAH3 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 D15 to D0 tAS3 tAH2 tRSD2 tRSD1 RD Read (RDNn = 0) tRDS2 tRDH2 tAC4 D15 to D0 tAS4 tAH3 tWRD1 HWR, LWR tWDD Write tWRD2 tWDS3 tWSW2 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 T1 T1 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 AS tRSD2 RD tAA1 tRDS2 tRDH2 Read D15 to D0 HWR, LWR Figure 25.13 Burst ROM Access Timing: One-State Burst Access R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 T3 T1 T2 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 tAH1 tAS1 tASD AS tASD tRSD2 RD Read tAA3 tRDS2 tRDH2 D15 to D0 HWR, LWR Figure 25.14 Burst ROM Access Timing: Two-State Burst Access Page 1256 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tr Tp Tc1 Tc2 φ tAD tAD A23 to A0 tAS3 RAS5 to RAS2 tCSD3 tAH1 tCSD2 tAS2 tPCH2 tAH2 tCASD1 tCASD1 UCAS tCASW1 LCAS tOED1/ tOED1B tOED1/ tOED1B tAC1 OE, RD Read HWR tAA3 tRDS2 tRDH2 tAC4 D15 to D0 OE, RD tWRD2 Write tWCS1 tWCH1 tWRD2 HWR tWDD tWDS1 tWDH2 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAS
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tp Tr Tc1 Tcw Tcwp Tc2 φ A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read HWR D15 to D0 UCAS, LCAS OE, RD Write HWR D15 to D0 AS tWTS tWTH tWTS tWTH WAIT DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Tcw: Wait cycle inserted by programmable wait function Tcwp: Wait cycle inserted by pin wait function Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Tp Section 25 Electrical Characteristics Tr Tc1 Tc2 Tc1 Tc2 φ A23 to A0 RAS5 to RAS2 tCPW1 UCAS LCAS OE, RD Read HWR tAC3 D15 to D0 OE, RD Write tRCH HWR tRCS1 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timing: when RAST = 0 Figure 25.17 DRAM Access Timing: Two-State Burst Access R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tp Tr Tc1 Tc3 Tc2 φ tAD tAD A23 to A0 tAS2 RAS5 to RAS2 tCSD3 tAH2 tCSD1 tPCH1 tAS3 tAH3 tCASD1 tCASD2 UCAS tCASW2 LCAS tOED2/ tOED2B tOED1/ tOED1B tAC2 OE, RD Read HWR tAA5 tRDS2 tRDH2 tAC7 D15 to D0 OE, RD Write tWRD2 tWCS2 tWCH2 tWRD2 HWR tWDD tWDS2 tWDH3 D15 to D0 AS tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 0 and EDDS = 0 RAS timin
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H8S/2426, H8S/2426R, H8S/2424 Group Tp Section 25 Electrical Characteristics Tr Tc1 Tc2 Tc3 Tc1 Tc2 Tc3 φ A23 to A0 RAS5 to RAS0 tCPW2 UCAS LCAS OE, RD Read HWR tAC8 D15 to D0 OE, RD Write tRCH HWR tRCS2 D15 to D0 AS DACK0, DACK1 EDACK2, EDACK3 Note: DACK and EDACK timing: when DDS = 1 and EDDS = 1 RAS timing: when RAST = 1 Figure 25.19 DRAM Access Timing: Three-State Burst Access R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics TRp TRc1 TRr TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 tCSR1 tCASD1 tCASD1 UCAS, LCAS OE Figure 25.20 CAS-Before-RAS Refresh Timing TRp TRrw TRr TRc1 TRcw TRc2 φ tCSD1 tCSD2 RAS5 to RAS2 UCAS, LCAS tCSR2 tCASD1 tCASD1 OE Figure 25.21 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion) Page 1262 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Self-refresh TRp TRr TRc TRc DRAM access TRp Tp Tr φ tCSD2 tCSD2 RAS5 to RAS2 tRPS2 tCASD1 tCASD1 UCAS, LCAS OE Figure 25.22 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh TRp TRr TRc TRc TRp DRAM access Tp Tr φ tCSD2 RAS5 to RAS2 tCASD1 tCSD2 tRPS1 tCASD1 UCAS, LCAS OE Figure 25.23 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tBREQS tBREQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 25.24 External Bus Release Timing φ BACK tBRQOD tBRQOD BREQO Figure 25.25 External Bus Request Output Timing Page 1264 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tr Tp Tc1 Tw Tc2 φ SDRAMφ tAD2 Address bus Precharge-sel RAS tCSD4 tCSD4 tCSD4 CAS Read tCSD4 tCSD4 tCSD4 WE CKE tDQMD High tDQMD DQMU, DQML tRDS3 tRDH3 Data bus tCSD4 tCSD4 RAS tCSD4 CAS tCSD4 tCSD4 tCSD4 WE tCSD4 tCSD4 Write CKE High tDQMD DQMU, DQML tDQMD tWDD Data bus tWDH4 Figure 25.26 Synchronous DRAM Basic Access Timing (CAS Latency 2) R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics TRp TRr Software standby TRr2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED/ tCKEDB CKE tCKED/ tCKEDB Figure 25.27 Synchronous DRAM Self-Refresh Timing Page 1266 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Tp Section 25 Electrical Characteristics Tr Tc1 Tc2 TRr Ttp2 φ SDRAMφ Address bus Precharge-sel RAS CAS WE tCKED/ tCKEDB tCKED/ tCKEDB CKE DQMU, DQML Data bus DACK or EDACK Figure 25.28 Read Data: Two-State Expansion (CAS Latency 2) R01UH0310EJ0500 Rev. 5.
PAGE 1298
Section 25 Electrical Characteristics 25.3.4 H8S/2426, H8S/2426R, H8S/2424 Group DMAC and EXDMAC Timing The DMAC and EXDMAC timings are shown below. Page 1268 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1299
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tma1 Tma2 T1 T2 φ tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD tAC2 Read (RDNn=0) tAA6 tMAD tMAS1 tMAH tRDS2 A15 to A0 AD15 to AD0 tRDH2 D15 toD0 tWRD2 tWRD2 HWR, LWR Write tWSW tMAD AD15 to AD0 tWDD A15 to A0 tWDH1 D15 toD0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.29 Multiplexed Bus Timing: Data Two-State Access R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tma1 Tmaw Tma2 T1 T2 Tw T3 φ tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD Read (RDNn=0) tMAD tMAS2 AD15 to AD0 tRDS2 tRDH2 tMAH A15 to A0 D15 to D0 tWRD1 tWRD2 HWR, LWR Write tWDD tWDS1 tMAD AD15 to AD0 tWDH1 D15 to D0 A15 to A0 tWTS tWTH tWTS tWTH WAIT Figure 25.30 Multiplexed Bus Timing: Data Three-State Access, One Wait (With address wait: when ADDEX = 1) Page 1270 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1301
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.31 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.32 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access Page 1272 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1303
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 or T3 φ tTED tTED tETED tETED TEND0, TEND1 ETEND2, ETEND3 Figure 25.33 DMAC and EXDMAC, TEND/ETEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 tEDRQS tEDRQH EDREQ2, EDREQ3 Figure 25.34 DMAC and EXDMAC, DREQ/EDREQ Input Timing φ tEDRKD tEDRKD EDRAK2, EDRAK3 Figure 25.35 EXDMAC, EDRAK Output Timing R01UH0310EJ0500 Rev. 5.
PAGE 1304
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.3.5 Timing of On-Chip Peripheral Modules The on-chip peripheral module timings are shown below. T1 T2 φ tPRS tPRH Ports 1 to 6, 8, 9, A to J (read) tPWD Ports 1 to 3, 6, 8, P53 to P50, ports A to J (write) Figure 25.36 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 25.37 PPG Output Timing Page 1274 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA11, TIOCB0 to TIOCB11, TIOCC0, TIOCC3, TIOCC6, TIOCC9, TIOCD0, TIOCD3, TIOCD6, and TIOCD9 Figure 25.38 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKH tTCKWL tTCKWH Figure 25.39 TPU Clock Input Timing R01UH0310EJ0500 Rev. 5.
PAGE 1306
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tTMOD TMO0, TMO1 Figure 25.40 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 25.41 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 25.42 8-Bit Timer Reset Input Timing Page 1276 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1307
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tWOVD tWOVD WDTOVF Figure 25.43 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK4 tScyc Figure 25.44 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transmit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 25.45 SCI Input/Output Timing: Synchronous Mode φ tTRGS ADTRG0, ADTRG1 Figure 25.46 A/D Converter External Trigger Input Timing R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics VIH SDA0 to SDA1 VIL tBUF tSCLH tSTAH SCL0 to SCL1 P* S* tSf tSTOS Sr* tSCLL tSr P* tSDAS tSCL Note: tSP tSTAS tSDAH S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 25.
PAGE 1309
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics SCS (output) tTD tFALL tHI tLEAD tRISE tLAG SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO tSUcyc SSO (output) tOH tOD SSI (input) tSU tH Figure 25.49 SSU Timing (Master, CPHS = 0) SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO tSUcyc SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tSUcyc tLO SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 25.51 SSU Timing (Slave, CPHS = 0) Page 1280 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.4 Electrical Characteristics for H8S/2426 Group (5-V Version) 25.4.1 Absolute Maximum Ratings Table 25.26 lists the absolute maximum ratings. Table 25.26 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +6.5 V Input voltage (except ports 4, 9, and 2, Vin P32 to P35, P50 and P51, and PJ0 to PJ2) −0.3 to VCC +0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.4.2 DC Characteristics Table 25.27 DC Characteristics (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1 Typ. Max. Test Unit Conditions ⎯ ⎯ V ⎯ VCC × 0.7 V ⎯ ⎯ V VCC × 0.9 ⎯ VCC +0.3 V RES, NMI, FWE VCC × 0.9 ⎯ VCC +0.3 V EXTAL VCC × 0.7 ⎯ VCC +0.3 V P14 to P17* , P24 to P26*5, 3 port 3* , P50 to P53*3, ports 6*3 and 8*3, 3 ports A to J* VCC × 0.
PAGE 1313
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions Output high All output pins voltage VOH VCC − 0.3 ⎯ ⎯ V IOH = −200 μA VCC − 0.5 ⎯ ⎯ V IOH = −1 mA VCC − 0.8 ⎯ ⎯ V IOH = −2 mA ⎯ ⎯ 0.4 V IOL = 4.0 mA ⎯ ⎯ 0.4 V IOL = 8.0 mA ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Ports 4 and 9 ⎯ ⎯ 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.28 DC Characteristics (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1 Test Conditions Item Symbol Min. Typ. Max. Unit Three-state Ports 1 to 3, leakage current P50 to P53, (off state) ports 6 and 8, ports A to I | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Input pull-up MOS current −Ip 10 ⎯ 300 μA VCC = 4.5 to 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 5.2 (mA) + 1.96 (mA/(MHz)) × f (normal operation) ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode) 5. Applied when RES is low at power-on. Table 25.29 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V* Item Symbol Min. Typ.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.4.3 AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, EXDMAC, and onchip peripheral functions. (1) Clock Timing Table 25.30 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3V RL C=50pF: Ports A to J C=30pF: Ports 1 to 3, P50 to P52, and ports 6 and 8. RL=2.4kΩ RH=12kΩ Output timing test level 2.5V: (Vcc=4.5 to 5.5V) LSI output pin C RH Figure 25.52 Output Load Circuit (2) Control Signal Timing Table 25.31 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (3) Bus Timing Table 25.32 Bus Timing (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Max. Test Unit Conditions 20 ns tAS1 0.5 × tcyc −13 ⎯ ns tAS2 1.0 × tcyc −13 ⎯ ns Address setup time 3 tAS3 1.5 × tcyc −13 ⎯ ns Address setup time 4 tAS4 2.0 × tcyc −13 ⎯ ns Address hold time 1 tAH1 0.5 × tcyc −8 ⎯ ns Address hold time 2 tAH2 1.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Symbol Min. Counter address read data access time 1 tAA1 ⎯ 1.0 × tcyc − 25 ns Counter address read data access time 2 tAA2 ⎯ 1.5 × tcyc − 25 ns Counter address read data access time 3 tAA3 ⎯ 2.0 × tcyc − 25 ns Counter address read data access time 4 tAA4 ⎯ 2.5 × tcyc − 25 ns Counter address read data access time 5 tAA5 ⎯ 3.0 × tcyc − 25 ns Counter address read data access time 6 tAA6 ⎯ 4.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.33 Bus Timing (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Test Conditions Item Symbol Min. Max. Unit WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.5 × tcyc −13 ⎯ ns Write data delay time tWDD ⎯ 23 ns Write data setup time 1 tWDS1 0.
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H8S/2426, H8S/2426R, H8S/2424 Group (4) Section 25 Electrical Characteristics DMAC and EXDMAC Timing Table 25.34 DMAC and EXDMAC Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 25.70 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 ns Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (5) Timing of On-Chip Peripheral Modules Table 25.35 Timing of On-Chip Peripheral Modules Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions 40 ns Figure 25.74 tPWD ⎯ Input data setup time tPRS 25 ⎯ ns Input data hold time tPRH 25 ⎯ ns PPG Pulse output delay time tPOD ⎯ 40 ns Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 25.84 IIC2 SCL input cycle time tSCL 12 tcyc +600 ⎯ ns Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item SCS hold time SSU* Master Symbol Min. Max. Unit Test Conditions tLAG 2.5 ⎯ tcyc 2.5 ⎯ Figures 25.86 to 25.89 ⎯ 40 ⎯ 40 Slave Note Master Data output hold time Master tOD Slave tOH Slave −5 ⎯ 0 ⎯ 2.5 ⎯ 2.5 ⎯ ns ns Continuous Master transmit delay time Slave tTD tcyc Slave access time tSA ⎯ 1 tcyc Slave out release time tREL ⎯ 1 tcyc Figures 25.88 and 25.
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H8S/2426, H8S/2426R, H8S/2424 Group 25.4.5 Section 25 Electrical Characteristics D/A Conversion Characteristics Table 25.37 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 8 8 8 Bit Conversion time ⎯ ⎯ 10 μs Absolute accuracy ⎯ ±1.0 ±2.0 LSB 2 MΩ resistive load ⎯ ⎯ ±1.0 LSB 4 MΩ resistive load 25.4.
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Section 25 Electrical Characteristics Notes: H8S/2426, H8S/2426R, H8S/2424 Group 1. When programming is to be performed multiple times on a system, reduce the effective number of programming operations by shifting the writing addresses in sequence and so on until the remaining blank area is as small as possible and only then erasing the entire block once.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.5 Electrical Characteristics for H8S/2424 Group (5-V Version) 25.5.1 Absolute Maximum Ratings Table 25.39 lists the absolute maximum ratings. Table 25.39 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC −0.3 to +6.5 V Input voltage (except ports 4, 9, and 2, Vin P32 to P35, P50 and P51, and P81 and P83) −0.3 to VCC +0.
PAGE 1328
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.5.2 DC Characteristics Table 25.40 DC Characteristics (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1 Typ. Max. Test Unit Conditions ⎯ ⎯ V ⎯ VCC × 0.7 V ⎯ ⎯ V VCC × 0.9 ⎯ VCC +0.3 V VCC × 0.7 ⎯ VCC +0.3 V P10 to P11* , P14 to P17*5, 5 P24 to P26* , 3 port 3* , P50 to P53*3, 3 port 8* , ports A 3 to G* VCC × 0.8 ⎯ VCC +0.3 V Ports 4 and 9 VCC × 0.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Typ. Max. Test Unit Conditions Output high All output pins voltage VOH VCC − 0.3 ⎯ ⎯ V IOH = −200 μA VCC − 0.5 ⎯ ⎯ V IOH = −1 mA VCC − 0.8 ⎯ ⎯ V IOH = −2 mA ⎯ ⎯ 0.4 V IOL = 4.0 mA ⎯ ⎯ 0.4 V IOL = 8.0 mA ⎯ ⎯ 10.0 μA STBY, NMI, MD2 to MD0 ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Port 4, Port 9 ⎯ ⎯ 1.
PAGE 1330
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.41 DC Characteristics (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1 Item Symbol Min. Typ. Max. Unit Test Conditions Three-state leakage current (off state) Ports 1 to 3, P50 to P53, port 8, ports A to G | ITSI | ⎯ ⎯ 1.0 μA Vin = 0.5 to VCC −0.5 V Input pull-up MOS current Ports A to E −Ip 10 ⎯ 300 μA VCC = 4.0 to 5.
PAGE 1331
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3. The values are for VRAM ≤ VCC < 4.5 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V. 4. ICC depends on VCC and f as follows: ICCmax = 5.2 (mA) + 1.96 (mA/(MHz)) × f (normal operation) ICCmax = 2.6 (mA) + 1.28 (mA/(MHz)) × f (sleep mode) 5. Applied when RES is low at power-on. Table 25.42 Permissible Output Currents Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V* Item Symbol Min. Typ.
PAGE 1332
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.5.3 AC Characteristics The following shows the timings of the clock, control signals, bus, DMAC, and on-chip peripheral functions. (1) Clock Timing Table 25.43 Clock Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Clock cycle time tcyc 30.3 125 ns Figure 25.
PAGE 1333
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 3V RL C=50pF: Ports A to G C=30pF: Ports 1 to 3, P50 to P53, and port 8 RL=2.4kΩ RH=12kΩ Output timing test level 2.5V: (Vcc = 4.5 to 5.5V) LSI output pin C RH Figure 25.53 Output Load Circuit (2) Control Signal Timing Table 25.44 Control Signal Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max.
PAGE 1334
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (3) Bus Timing Table 25.45 Bus Timing (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Address delay time tAD ⎯ 20 ns Address setup time 1 tAS1 0.5 × tcyc −13 ⎯ ns Figures 25.58 to 25.68 Address setup time 2 tAS2 1.0 × tcyc −13 ⎯ ns Address setup time 3 tAS3 1.
PAGE 1335
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Table 25.45 Bus Timing (2) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions WR delay time 1 tWRD1 ⎯ 15 ns WR delay time 2 tWRD2 ⎯ 15 ns Figures 25.58 to 25.68 WR pulse width 1 tWSW1 1.0 × tcyc −13 ⎯ ns WR pulse width 2 tWSW2 1.
PAGE 1336
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics (4) DMAC Timing Table 25.46 DMAC Timing Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions DREQ setup time tDRQS 25 ⎯ ns Figure 25.72 DREQ hold time tDRQH 10 ⎯ TEND delay time tTED ⎯ 18 Figure 25.71 DACK delay time 1 tDACD1 ⎯ 18 Figures 25.69 and 25.
PAGE 1337
H8S/2426, H8S/2426R, H8S/2424 Group (5) Section 25 Electrical Characteristics Timing of On-Chip Peripheral Modules Table 25.47 Timing of On-Chip Peripheral Modules Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Symbol Min. Max. Unit Test Conditions Figure 25.74 tPWD ⎯ 40 ns Input data setup time tPRS 25 ⎯ ns Input data hold time tPRH 25 ⎯ ns PPG Pulse output delay time tPOD ⎯ 40 ns Figure 25.
PAGE 1338
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item Symbol Min. Max. Unit Test Conditions A/D converter Trigger input setup time tTRGS 30 ⎯ ns Figure 25.84 IIC2 SCL input cycle time tSCL 12 tcyc +600 ⎯ ns Figure 25.
PAGE 1339
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Item SCS hold time SSU* Master Symbol Min. Max. Unit Test Conditions tLAG 2.5 ⎯ tcyc 2.5 ⎯ Figures 25.86 to 25.89 ⎯ 40 ⎯ 40 Slave Note Master Data output hold time Master tOD Slave tOH Slave −5 ⎯ 0 ⎯ 2.5 ⎯ 2.5 ⎯ ns ns Continuous Master transmit delay time Slave tTD tcyc Slave access time tSA ⎯ 1 tcyc Slave out release time tREL ⎯ 1 tcyc Figures 25.88 and 25.
PAGE 1340
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.5.5 D/A Conversion Characteristics Table 25.49 D/A Conversion Characteristics Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, φ = 8 MHz to 33 MHz Item Min. Typ. Max. Unit Resolution 8 8 8 Bit Conversion time ⎯ ⎯ 10 μs Absolute accuracy ⎯ ±1.0 ±2.0 LSB 2 MΩ resistive load ⎯ ⎯ ±1.0 LSB 4 MΩ resistive load 25.5.
PAGE 1341
H8S/2426, H8S/2426R, H8S/2424 Group Notes: Section 25 Electrical Characteristics 1. In the system where multiple programming are executed, erase once so as to effectively diminish the programming times after having written with leaving the blank area as least as possible by shifting writing address one by one. For example, if 16 bytes per 1 set is being programmed, erase once after maximum 256 sets of programming has been done, which diminish the effective programming times.
PAGE 1342
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.6 Timing Charts (5-V Version) 25.6.1 Clock Timing The clock timings are shown below. tcyc tCH tCf φ tCL tCr Figure 25.54 System Clock Timing EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 25.55 (1) Oscillation Settling Timing Page 1312 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1343
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Oscillator φ NMI NMIEG SSBY NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down state) Oscillation stabilization time tOSC2 SLEEP instruction Figure 25.55 (2) Oscillation Settling Timing R01UH0310EJ0500 Rev. 5.
PAGE 1344
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics 25.6.2 Control Signal Timing The control signal timings are shown below. φ tRESS tRESS RES tRESW Figure 25.56 Reset Input Timing φ tNMIS tNMIH NMI tNMIW tIRQW IRQi (i = 0 to 15)* tIRQS tIRQH IRQ (edge input) tIRQS IRQ (level input) Note: * SSIER setting is necessary to clear software standby mode. Figure 25.57 Interrupt Input Timing Page 1314 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1345
H8S/2426, H8S/2426R, H8S/2424 Group 25.6.3 Section 25 Electrical Characteristics Bus Timing The bus timings are shown below. T2 T1 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC5 tAA2 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 tAA3 D15 to D0 tAS1 tWRD2 tWRD2 tAH1 HWR, LWR tWDD Write tWSW1 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
PAGE 1346
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T3 T2 φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tASD tAH1 AS tAS1 tRSD1 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 tAA4 D15 to D0 tAS1 tRSD1 tRSD2 RD Read (RDNn = 0) tRDS2 tAC4 tRDH2 tAA5 D15 to D0 tAS2 tWRD2 tAH1 tWRD1 HWR, LWR tWDS1 tWDD Write tWSW2 tWDH1 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
PAGE 1347
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD Read (RDNn = 1) D15 to D0 RD Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 25.60 Basic Bus Timing: Three-State Access, One Wait R01UH0310EJ0500 Rev. 5.
PAGE 1348
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 Th T2 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tAH1 tASD tASD AS tAS3 tAH3 tRSD1 tRSD1 RD Read (RDNn = 1) tAC5 tRDS1 tRDH1 tRSD1 tRSD2 D15 to D0 tAS3 tAH2 RD Read (RDNn = 0) tAC2 tRDS2 tRDH2 D15 to D0 tAS3 tWRD2 tWRD2 tAH3 HWR, LWR tWDD Write tWDS2 tWSW1 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
PAGE 1349
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Th T1 T2 T3 Tt φ tAD A23 to A0 tCSD1 CS7 to CS0 tAS1 tASD tAH1 tASD AS tAS3 tRSD1 tAH3 tRSD1 RD Read (RDNn = 1) tRDS1 tRDH1 tAC6 D15 to D0 tAS3 tAH2 tRSD2 tRSD1 RD Read (RDNn = 0) tRDS2 tRDH2 tAC4 D15 to D0 tAS4 tAH3 tWRD1 HWR, LWR tWDD Write tWRD2 tWDS3 tWSW2 tWDH3 D15 to D0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.
PAGE 1350
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 T1 T1 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 AS tRSD2 RD tAA1 tRDS2 tRDH2 Read D15 to D0 HWR, LWR Figure 25.63 Burst ROM Access Timing: One-State Burst Access Page 1320 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1351
H8S/2426, H8S/2426R, H8S/2424 Group T1 Section 25 Electrical Characteristics T2 T3 T1 T2 φ A23 to A6, A0 tAD A5 to A1 CS1, CS0 tAH1 tAS1 tASD AS tASD tRSD2 RD Read tRDS2 tRDH2 tAA3 D15 to D0 HWR, LWR Figure 25.64 Burst ROM Access Timing: Two-State Burst Access R01UH0310EJ0500 Rev. 5.
PAGE 1352
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tBREQS tBREQS BREQ tBACD tBACD BACK tBZD tBZD A23 to A0 CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 25.65 External Bus Release Timing φ BACK tBRQOD tBRQOD BREQO Figure 25.66 External Bus Request Output Timing Page 1322 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1353
H8S/2426, H8S/2426R, H8S/2424 Group 25.6.4 Section 25 Electrical Characteristics DMAC and EXDMAC Timing The DMAC and EXDMAC timings are shown below. R01UH0310EJ0500 Rev. 5.
PAGE 1354
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics Tma1 Tma2 T1 T2 φ tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD tAC2 Read (RDNn=0) tAA6 tMAD tMAS1 tMAH tRDS2 A15 to A0 AD15 to AD0 tRDH2 D15 toD0 tWRD2 tWRD2 HWR, LWR Write tWSW tMAD AD15 to AD0 tWDD A15 to A0 tWDH1 D15 toD0 tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.67 Multiplexed Bus Timing: Data Two-State Access Page 1324 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1355
H8S/2426, H8S/2426R, H8S/2424 Group Tma1 Section 25 Electrical Characteristics Tmaw Tma2 T1 T2 Tw T3 φ tAD A23 to A0 tCSD1 CS7, CS6 tAHD AH tRSD1 tRSD2 RD Read (RDNn=0) tMAD tMAS2 tRDS2 tRDH2 tMAH A15 to A0 AD15 to AD0 D15 to D0 tWRD1 tWRD2 HWR, LWR Write tWDD tWDS1 tMAD AD15 to AD0 tWDH1 D15 to D0 A15 to A0 tWTS tWTH tWTS tWTH WAIT Figure 25.68 Multiplexed Bus Timing: Data Three-State Access, One Wait (With address wait: when ADDEX = 1) R01UH0310EJ0500 Rev. 5.
PAGE 1356
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.69 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access Page 1326 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1357
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 tEDACD1 tEDACD2 DACK0, DACK1 EDACK2, EDACK3 Figure 25.70 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access R01UH0310EJ0500 Rev. 5.
PAGE 1358
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics T1 T2 or T3 φ tTED tTED tETED tETED TEND0, TEND1 ETEND2, ETEND3 Figure 25.71 DMAC and EXDMAC, TEND/ETEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 tEDRQS tEDRQH EDREQ2, EDREQ3 Figure 25.72 DMAC and EXDMAC, DREQ/EDREQ Input Timing φ tEDRKD tEDRKD EDRAK2, EDRAK3 Figure 25.73 EXDMAC, EDRAK Output Timing Page 1328 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1359
H8S/2426, H8S/2426R, H8S/2424 Group 25.6.5 Section 25 Electrical Characteristics Timing of On-Chip Peripheral Modules The on-chip peripheral module timings are shown below. T1 T2 φ tPRS tPRH Ports 1 to 6, 8, 9, A to J (read) tPWD Ports 1 to 3, 6, 8, P53 to P50, ports A to J (write) Figure 25.74 I/O Port Input/Output Timing φ tPOD PO15 to PO0 Figure 25.75 PPG Output Timing R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA11, TIOCB0 to TIOCB11, TIOCC0, TIOCC3, TIOCC6, TIOCC9, TIOCD0, TIOCD3, TIOCD6, and TIOCD9 Figure 25.76 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKH tTCKWL tTCKWH Figure 25.77 TPU Clock Input Timing Page 1330 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1361
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tTMOD TMO0, TMO1 Figure 25.78 8-Bit Timer Output Timing φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 25.79 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 25.80 8-Bit Timer Reset Input Timing R01UH0310EJ0500 Rev. 5.
PAGE 1362
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics φ tWOVD tWOVD WDTOVF Figure 25.81 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK4 tScyc Figure 25.82 SCK Clock Input Timing SCK0 to SCK4 tTXD TxD0 to TxD4 (transmit data) tRXS tRXH RxD0 to RxD4 (receive data) Figure 25.83 SCI Input/Output Timing: Synchronous Mode φ tTRGS ADTRG0, ADTRG1 Figure 25.84 A/D Converter External Trigger Input Timing Page 1332 of 1384 R01UH0310EJ0500 Rev. 5.
PAGE 1363
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics VIH SDA0 to SDA1 VIL tBUF tSCLH tSTAH SCL0 to SCL1 P* S* tSf tSTOS Sr* tSCLL tSr P* tSDAS tSCL Note: tSP tSTAS tSDAH S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Retransmit start condition Figure 25.
PAGE 1364
H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics SCS (output) tTD tFALL tHI tLEAD tRISE tLAG SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO tSUcyc SSO (output) tOH tOD SSI (input) tSU tH Figure 25.87 SSU Timing (Master, CPHS = 0) SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO tSUcyc SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 25.
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H8S/2426, H8S/2426R, H8S/2424 Group Section 25 Electrical Characteristics SCS (input) tLEAD tFALL tHI tRISE tLAG tTD SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tSUcyc tLO SSO (input) tSU tH tREL SSI (output) tSA tOH tOD Figure 25.89 SSU Timing (Slave, CPHS = 0) R01UH0310EJ0500 Rev. 5.
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Section 25 Electrical Characteristics Page 1336 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
PAGE 1367
H8S/2426, H8S/2426R, H8S/2424 Group Appendix Appendix A. Port States in Each Processing State Table A.
PAGE 1368
H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode P51/BREQ-B 1, 2, 3, 4, 7 P50/ BREQO-B 1, 2, 3, 4, 7 Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode T T T T [BREQ-B input] T [BREQ-B input] BREQ-B [BREQ-B input] BREQ-B [Other than the above] Keep [Other than the above] Keep [Other than the above] I/O port [BREQO-B output] [BREQO-B output] [BREQO-B output] BREQO-B BREQO-B BREQO-B [Other than the above]
PAGE 1369
H8S/2426, H8S/2426R, H8S/2424 Group Port Name Pin Name MCU Operating Mode PA4/A20 1, 2 Appendix Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode L T T [Address output] A20 to A16 [Address output] T [Address output] A20 to A16 [Other than the above] Keep [Other than the above] I/O port T [Address output] A15 to A8 [Address output] T [Address output] A15 to A8 [Other than the above] Keep [Other than the above] I/O port PA3/A19 [OPE
PAGE 1370
H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode Port C 1, 2 Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode L T T [Address output] A7 to A0 [Address output] T [Address output] A7 to A0 [Other than the above] Keep [Other than the above] I/O port [OPE = 0] T [OPE = 1] Keep 3, 4, 7 T T [Address output, OPE = 0] T [Address output, OPE = 1] Keep [Other than the above] Keep Port D Port E 1, 2, 4 T T
PAGE 1371
H8S/2426, H8S/2426R, H8S/2424 Group Port Name Pin Name Port E PF7/φ PF6/AS/AH MCU Operating Mode Appendix Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode T T Keep Keep I/O port 16-bit T bus T [Data bus, address/data multiplexed bus] T [Data bus, address/data multiplexed bus] T [Other than the above] Keep [Other than the above] Keep [Data bus, address/data multiplexed bus] D7 to D0, AD7 to AD0 [Clock output] H [Clock output] Clock o
PAGE 1372
H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode PF3/LWR Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode 1, 2, 4 H T 3, 7 T [LWR output] T [LWR output] LWR [Other than the above] Keep [Other than the above] I/O port [LCAS, DQML output, OPE = 0] T [LCAS, DQML output] T [LCAS, DQML output] LCAS, DQML [LCAS, DQML output, OPE = 1] H [Other than the above] Keep [Other than the above] I/O port [UCAS, DQ
PAGE 1373
H8S/2426, H8S/2426R, H8S/2424 Group Port Name Pin Name PG5/ BACK-A PG4/ BREQO-A PG3/CS3/ 2 RAS3* / 1 CAS* MCU Operating Mode 1, 2, 3, 4, 7 1, 2, 3, 4, 7 1, 2, 3, 4, 7 Appendix Reset Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode T T T T T T [BACK-A output] BACK-A [BACK-A output] BACK-A [BACK-A output] BACK-A [Other than the above] Keep [Other than the above] Keep [Other than the above] I/O port [BREQO-A output] [BREQO-A output] [BREQO-
PAGE 1374
H8S/2426, H8S/2426R, H8S/2424 Group Appendix MCU Operating Mode Port Name Pin Name 2 PH3/OE-A* / 1, 2, 3, 4, 7 1 CKE-A* / CS7 Reset Hardware Standby Software Standby Bus Release Mode Mode State T T [OE-A, CS, CKE-A output, OPE = 0] T [OE-A output, OPE = 1] H Program Execution State Sleep Mode [OE-A, CS, CKE-A output] T [OE-A, CKE-A output] OE-A, CKE-A [Other than the above] Keep [CS output] CS [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [CS out
PAGE 1375
H8S/2426, H8S/2426R, H8S/2424 Group Port Name Pin Name PH1/CS5/ 2 RAS5* 1 SDRAMφ* MCU Operating Mode 1, 2, 3, 4, 7 Reset [H8S/ 2426R Group] Clock output [H8S/ 2426 Group] T Appendix Hardware Standby Software Standby Bus Release Mode Mode State Program Execution State Sleep Mode [H8S/2426R [SDPSTP = 0 in [SDPSTP = 0 in [SDPSTP = 0 in Group] H8S/2426R Group] H8S/2426R Group] H8S/2426R Group] L L Clock output Clock output [H8S/2426 Group] T [SDPSTP = 1 in H8S/2426R Group, or H8S/2426 Group, CS output,
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Appendix H8S/2426, H8S/2426R, H8S/2424 Group [Legend] H: High-level L: Low-level Keep: Input ports become high-impedance, and output ports retain their state. T: High-impedance DDR: Data direction register OPE: Output port enable Notes: 1. Not supported in the H8S/2426 Group. 2. Not supported in the 5-V version. 3. Low output if a watchdog timer overflow occurs when WT/IT is set to 1. Page 1346 of 1384 R01UH0310EJ0500 Rev. 5.
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Table A.
PAGE 1378
H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name P50/ BREQO-B MCU Operating Mode Reset Hardware Standby Mode 1, 2, 3, 4, 7 T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [BREQO-B output] BREQO-B [BREQO-B output] BREQO-B [BREQO-B output] BREQO-B [Other than the above] Keep [Other than the above] Keep [Other than the above] I/O port Port 8 1, 2, 3, 4, 7 T T Keep Keep I/O port P95/DA3 1, 2, 3, 4, 7 T T [DAOE3 = 1] Keep Keep Input por
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode PA6/A22 1, 2, 3, 4, 7 T T PA5/A21 Software Standby Mode Bus Release State [Address output, [Address output] OPE = 0] T T [Other than the [Address output, above] OPE = 1] Keep Keep Program Execution State Sleep Mode [Address output] A22 to A21 [Other than the above] I/O port [Other than the above] Keep PA4/A20 1, 2 L T PA3/A19 [OPE = 0] T T [Address output] A20 to A16 [OPE = 1
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode Port B 1, 2 L T Software Standby Mode Bus Release State [OPE = 0] T T Program Execution State Sleep Mode [Address output] A15 to A8 [OPE = 1] Keep 4 T T [Address output, [Address output] OPE = 0] T T [Other than the [Address output, above] OPE = 1] Keep Keep [Address output] A15 to A8 [Other than the above] I/O port [Other than the above] Keep 3, 7 T T [Address output, [Addre
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode Port C 1, 2 L T Software Standby Mode Bus Release State [OPE = 0] T T Program Execution State Sleep Mode [Address output] A7 to A0 [OPE = 1] Keep 4 T T [Address output, [Address output] OPE = 0] T T [Other than the [Address output, above] OPE = 1] Keep Keep [Address output] A7 to A0 [Other than the above] I/O port [Other than the above] Keep 3, 7 T T [Address output, [Address
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name Port E PF7/φ PF6/AS MCU Operating Mode Reset Hardware Standby Mode Software Standby Mode Bus Release State Program Execution State Sleep Mode T T Keep Keep I/O port 1, 2, 4 8-bit bus 16-bit bus T T T T D7 to D0, AD7 to AD0 3, 7 8-bit bus T T Keep Keep I/O port 16-bit bus T T [Data bus, address/data multiplexed bus] T [Data bus, address/data multiplexed bus] T [Other than the above] Keep [Other than the above]
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode Reset Hardware Standby Mode PF3/LWR 1, 2, 4 H T 3, 7 T Software Standby Mode Bus Release State Program Execution State Sleep Mode [LWR output, OPE = 0] T [LWR output] T [LWR output] LWR [Other than the above] Keep [Other than the above] I/O port [LCAS output] T [LCAS output] LCAS [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [UCAS output] T [UCAS output] UC
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Port Name Pin Name MCU Operating Mode PF0/WAIT-A/ 1, 2, 3, 4, 7 1 OE-A* Reset Hardware Standby Mode T T Software Standby Mode Bus Release State Program Execution State Sleep Mode [WAIT-A input] T [WAIT-A input] T [WAIT-A input] WAIT-A [OE-A output] T [OE-A output, OPE = 0] T [OE-A output, OPE = 0] OE-A [Other than the above] Keep [Other than the above] I/O port [BREQ-A input] T [BREQ-A input] BREQ-A [BREQ-A input] BREQ-A [Other than the abo
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H8S/2426, H8S/2426R, H8S/2424 Group Port Name Pin Name PG3/CS3/ 1 RAS3* Appendix MCU Operating Mode Reset Hardware Standby Mode 1, 2, 3, 4, 7 T T PG2/CS2/ 1 RAS2* Software Standby Mode Bus Release State Program Execution State Sleep Mode [CS output, OPE = 0] T [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port [CS output] T [CS output] CS [Other than the above] Keep [Other than the above] I/O port H H* [CS output, OPE = 1] H PG1/CS1 [Other than
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix B. Package Dimensions JEITA Package Code P-LQFP144-20x20-0.50 RENESAS Code PLQP0144KA-A Previous Code 144P6Q-A / FP-144L / FP-144LV MASS[Typ.] 1.2g HD *1 D 108 73 109 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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H8S/2426, H8S/2426R, H8S/2424 Group JEITA Package Code P-TFLGA145-9x9-0.65 Appendix RENESAS Code PTLG0145JB-A Previous Code - MASS[Typ.] 0.15g D w S B E w S A x4 v y1 S A S y S e A ZD e N M L K J B H G F E D ZE C B Reference Symbol Dimension in Millimeters Min 9.0 E 9.0 1 2 3 4 5 6 7 φb 8 9 10 11 12 13 0.15 w 0.20 A 1.2 A1 b 0.65 0.30 0.35 0.40 0.08 x φxn S A B Max v e A Nom D y 0.1 y1 0.20 SD SE ZD 0.6 ZE 0.6 Figure B.
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix JEITA Package Code P-LQFP120-14x14-0.40 RENESAS Code PLQP0120LA-A Previous Code 120P6R-A / FP-120B / FP-120BV MASS[Typ.] 0.7g HD *1 D 90 61 60 91 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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H8S/2426, H8S/2426R, H8S/2424 Group JEITA Package Code P-LQFP120-16x16-0.50 Appendix RENESAS Code PLQP0120KA-A Previous Code — MASS[Typ.] 0.9g HD *1 D 90 61 60 91 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix C. Treatment of Unused Pins The treatments of unused pins are listed in table C.1 Table C.
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H8S/2426, H8S/2426R, H8S/2424 Group Appendix Pin Name Mode 1 PF7 • This pin is left open in the initial state for the φ output. PF6 • This pin is left open in the initial state for the AS output. PF5 • This pin is left open in the initial state for the RD output. PF4 • This pin is left open in the initial state for the HWR output. PF3 • This pin is left open in the initial state for the LWR output. PG0 • This pin is left open in the initial state for the CS0 output.
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Appendix Page 1362 of 1384 H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 Rev. 5.
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Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) 4.3 Reset 98 Amended A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 15 ms at power-up. To reset this LSI during operation, hold the RES pin low for at least 2 ms. 7.
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Item Page Revision (See Manual for Details) Table 7.4 DMAC Transfer Modes 348, 349 Amended Transfer Source • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmit data empty interrupt • SCI receive data full interrupt • A/D converter conversion end interrupt • External request • TPU channel 0 to 5 compare match/input capture A interrupt • SCI transmit data empty interrupt • SCI receive data full interrupt • A/D converter conversion end interrupt • External request 7.5.
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Item Page Revision (See Manual for Details) 10.1.5 Pin Functions 525 Notes amended (1) Pin Functions of H8S/2426 Group and H8S/2426R Group 3. When using as SCS0-A input, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other register setting. 4. When using as SCS0-A output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other register setting. 5. When using as SCS0-A input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'00 before other register setting.
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Item Page Revision (See Manual for Details) • 539 • P15/DACK1/ PO13/TIOCB1/ TCLKC/SSI0-A P14/DACK0/ PO12/TIOCA1/ SSO0-A 541 Notes amended 3. When using as SSI0-A input, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other register setting. 4. When using as SSI0-A output, set SSI0S1 and SSI0S0 in PFCR5 to B'00 before other register setting. Notes amended 2. When using as SSO0-A input, set SSO0S1 and SSO0S0 in PFCR5 to B'00 before other register setting. 3.
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Item Page Revision (See Manual for Details) • 556 • • P22/IRQ10-B/ PO2-A/ TIOCC3-A P21/IRQ9-B/ PO1-A/ TIOCB3-A P20/PO0-A/ TIOCA3-A/ IRQ8-B (2) Pin Functions of H8S/2424 Group • 557 558 561 P25/WAIT-B/ PO5-A/ TIOCB4-A/ TMO1-A • Modes 3 and 7 (EXPE = 0) • P24/PO4-A/ TIOCA4-A/ TMO0-A/ RxD4-A 563 R01UH0310EJ0500 Rev. 5.00 Sep 25, 2012 Notes amended 4. When using as PO2-A output, set PPGS in PFCR3 to 0 before other register setting. 5.
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Item • • • • Page Revision (See Manual for Details) 564 P23/PO3-A/ TIOCD3-A/ TMCI1-A/TxD4-A P22/PO2-A/ TIOCC3-A/ TMCI0-A P21/PO1-A/ TIOCB3-A/ TMRI1-A P20/PO0-A/ TIOCA3-A/ TMRI0-A 566 567 568 Notes amended 3. When using as PO3-A output, set PPGS in PFCR3 to 0 before other register setting. 4. When using as TIOCD3-A input/output, set TPUS in PFCR3 to 0 before other register setting. 5. When using as TMCI1-A input, set TMRS in PFCR3 to 0 before other register setting. 6.
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Item Page Revision (See Manual for Details) 10.5.5 Pin Functions 581 Notes amended • 4. When using as PO4-B output, set PPGS in PFCR3 to 1 before other register setting. 5. When using as TIOCA4-B input/output, set TPUS in PFCR3 to 1 before other register setting. 6. When using as TMO0-B output, set TMRS in PFCR3 to 1 before other register setting.
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Item Page Revision (See Manual for Details) • P61/IRQ9A/DREQ1/ TMRI1-A 590 P60/IRQ8A/DREQ0/ TMRI0-A 591 • Notes amended 3. When using as TMRI1-A input, set TMRS in PFCR3 to 0 before other register setting. Notes amended 3. When using as TMRI0-A input, set TMRS in PFCR3 to 0 before other register setting. 10.7.5 Pin Functions 596 Notes amended (1) Pin Functions of H8S/2426 Group and H8S/2426R Group 3. When using as PO5-B output, set PPGS in PFCR3 to 1 before other register setting. 4.
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Item Page Revision (See Manual for Details) (2) Pin Functions of H8S/2424 Group 601 • • • P85/SCK3/ PO5-B/ TIOCB4-B/ TMO1-B P83/PO3-B/ TIOCD3-B/ TMCI1-B/RxD3 P81/PO1-B/ TIOCB3-B/ TMRI1-B/TxD3 603 604 Notes amended 2. When using as PO5-B output, set PPGS in PFCR3 to 1 before other register setting. 3. When using as TIOCB4-B input/output, set TPUS in PFCR3 to 1 before other register setting. 4. When using as TMO1-B output, set TMRS in PFCR3 to 1 before other register setting. Notes amended 3.
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Item • • Page Revision (See Manual for Details) PA4/A20/IRQ4-A/ 618 SCS0-B PA3/A19/SCK4-B 620 Notes amended 2. When using as SCS0-B input, set SCS0S1 and SCS0S0 in PFCR5 to B'01 before other register setting. 3. When using as SCS0-B output, set SCS0S1 and SCS0S0 in PFCR5 to B'01 before other register setting. 4. When using as SCS0-B input/output, set SCS0S1 and SCS0S0 in PFCR5 to B'01 before other register setting.
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Item • Page Revision (See Manual for Details) 7 PF1/UCAS* / 6 DQMU* / IRQ14-A/ SSCK0-C (H8S/ 2426 Group and H8S/2426R Group) • Modes 3 and 7 (EXPE = 0) • PF1/CS5/ 5 UCAS* / SSCK0-C (H8S/ 2424 Group) • Modes 3 and 7 (EXPE = 0) • PF0/WAIT-A/ ADTRG0-B/ SCS0-C (H8S/ 2426 Group and H8S/2426R Group) • Modes 3 and 7 (EXPE = 0) • PF0/WAIT-A/ ADTRG0-B/ SCS0-C/ 8 OE-A* (H8S/2424 Group) • 667 669 671 673 Modes 3 and 7 (EXPE = 0) R01UH0310EJ0500 Rev. 5.00 Sep 25, 2012 Notes amended 2.
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Item Page Revision (See Manual for Details) 15.3.7 Serial Status Register (SSR) 887 Smart Card Interface Mode (When SMIF bit in SCMR is 1) Amended Bit Bit Name Description 2 TEND Timing to set this bit differs according to the register settings. GM = 0, BLK = 0: 12.5 etu after transmission GM = 0, BLK = 1: 11.5 etu after transmission GM = 1, BLK = 0: 11.0 etu after transmission GM = 1, BLK = 1: 11.0 etu after transmission Table 15.
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Item Page Revision (See Manual for Details) 17.3.5 A/D Control Register (ADCR_1) Unit 1 1006, Added 1007 Bit Bit Name Description 7 TRGS1 6 TRGS0 Enables A/D conversion start by external trigger 1 from TPU (units 0 and 1)* 0 EXTRGS 5 SCANE 4 SCANS 11: Scan mode. A/D conversion is performed 2 continuously for channels 1 to 8.* Notes: 1.
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Item Page Revision (See Manual for Details) 19.3.5 SS Status Register (SSSR) 1045, Deleted 1046 Bit Bit Name 6 ORER Description [Clearing condition] When writing 0 after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 hile the corresponding interrupt is enabled, be sure to ead the flag after writing 0 to it.
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Item Page Revision (See Manual for Details) Table 25.2 DC Characteristics (1) 1216, Added and amended 1217 Item Table 25.
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Item Page Revision (See Manual for Details) Table 25.15 DC Characteristics (1) 1233 Amended and added Item 6 Table 25.
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Index Numerics 16-Bit counter mode ............................... 844 16-Bit timer pulse unit (TPU)................. 701 8-Bit timer (TMR) .................................. 827 Bus controller (BSC)............................... 149 Bus release .............................................. 312 C A A/D conversion accuracy...................... 1018 A/D converter ......................................... 991 A/D converter activation......................... 783 Absolute accuracy..........................
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DMTEND1A .......................................... 131 DMTEND1B .......................................... 131 DRAM interface ............................. 208, 222 DTC vector table .................................... 485 Dual address mode.................................. 423 E Effective address extension ...................... 72 Ending DMA transfer ............................. 468 ERI0........................................................ 945 ERI1....................................................
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N Q NMI ........................................................ 146 NMI interrupt.......................................... 127 Nonlinearity error ................................. 1018 Non-overlapping pulse output ................ 819 Normal mode ...................... 49, 50, 363, 492 Normal transfer mode ............................. 430 Quantization error ................................. 1018 O Offset error ........................................... 1018 On-board programming .....................
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EDDAR .............................................. 411 EDMDR.............................................. 413 EDSAR............................................... 410 EDTCR............................................... 411 ETCR.................................................. 321 EXMSTPCR ..................................... 1148 ICCRA................................................ 960 ICCRB ................................................ 962 ICDRR................................................
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PORTE ............................................... 653 PORTF................................................ 660 PORTG ............................................... 676 PORTH ............................................... 684 RDNCR .............................................. 163 RDR.................................................... 870 REFCR ............................................... 182 RMMSTPCR .................................... 1149 RSR...................................................
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System control instructions ...................... 71 T TCI0V..................................................... 130 TCI1U............................................. 780, 781 TCI1V............................................. 780, 781 TCI2U............................................. 780, 781 TCI2V............................................. 780, 781 TCI3V............................................. 780, 781 TCI4U............................................. 780, 781 TCI4V...........................
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H8S/2426, H8S/2426R, H8S/2424 Group User’s Manual: Hardware Publication Date: Rev.1.00 Rev.5.
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http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
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H8S/2426, H8S/2426R, H8S/2424 Group R01UH0310EJ0500 (REJ09B0466-0350)