Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Page 938 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
15.7.8 Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and
CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 15.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
Specified pulse width
SCK
CKE0
Specified pulse width
Figure 15.31 Timing for Fixing Clock Output Level
When turning on the power or switching between Smart Card interface mode and software
standby mode, the following procedures should be followed in order to maintain the clock duty
cycle.
Powering On: To secure the clock duty cycle from power-on, the following switching procedure
should be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to Smart Card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.