Datasheet

Section 13 8-Bit Timers (TMR)
R01UH0310EJ0500 Rev. 5.00 Page 843 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.5.5 Timing of TCNT External Reset
TCNT is cleared at the rising edge, falling edge, low level, or high level of an external reset input,
depending on the settings of the CCLR1 and CCLR0 bits in TCR and the TMRIS bit in TCCR.
The clear pulse width must be at least 1.5 states for a single edge and at least 2.5 states for both
edges. Figure 13.9 shows the timing of this operation.
Clear signal
External reset
input pin
φ
TCNT N
H'00N – 1
Figure 13.9 Timing of Clearance by External Reset
13.5.6 Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 13.10
shows the timing of this operation.
OVF
Overflow signal
TCNT
φ
H'FF H'00
Figure 13.10 Timing of OVF Setting