Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Page 796 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
11.10.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 11.48 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
TGR address
TCNT
TGR write cycle
T
1
T
2
NM
TGR write data
TGR
N N + 1
Disabled
Figure 11.48 Contention between TGR Write and Compare Match