Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 464 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
φ pin EDREQ EDRAK EDACK Bus cycle CPU operation ETEND
1-block-size transfer period 1-block-size transfer period
Last transfer
in block
Last transfer
in block
2 bus cycles
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
External
space
External
space
External
space
External
space
External
space
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
CPU
cycle
External
space
Repeated Repeated
Figure 8.41 External Request/Cycle Steal Mode/Block Transfer Mode
(CPU Cycles/Single Address Mode/Low Level Sensing/BGUP = 0)