Datasheet
Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 463 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
φ pin
EDREQ
EDRAK
EDACK
Bus cycle
ETEND
Bus release Bus release
Last transfer
in block
1-block-size transfer period
Last block
Last transfer cycle3 cycles
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
EXDMA single
transfer cycle
Repeated Repeated
Bus
release
Figure 8.40 External Request/Cycle Steal Mode/Block Transfer Mode
(No Contention/Single Address Mode/Falling Edge Sensing/BGUP = 0)