Datasheet

Section 8 EXDMA Controller (EXDMAC)
R01UH0310EJ0500 Rev. 5.00 Page 437 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Figure 8.11 shows EDTCR update operations in normal transfer mode and block transfer mode.
23 0
0
EDTCR
Fixed
23 0
0
Before update
After update
23 0
1 to H'FFFFFF
EDTCR
–1
23 0
0 to H'FFFFFE
EDTCR
EDTCR in normal transfer mode
EDTCR in block transfer mode
Fixed
Before update After update
23 15 016
1 to H'FFFF
Block
size
EDTCR
–1
23 15 016
0
Block
size
23 15 016
0 to H'FFFE
Block
size
23 15 016
0
Block
size
Figure 8.11 EDTCR Update Operations in Normal Transfer Mode and
Block Transfer Mode
(4) EDA Bit in EDMDR
The EDA bit in EDMDR is written to by the CPU to control enabling and disabling of data
transfer, but may be cleared automatically by the EXDMAC due to the DMA transfer status. There
are also periods during transfer when a 0-write to the EDA bit by the CPU is not immediately
effective.
Conditions for EDA bit clearing by the EXDMAC include the following:
• When the EDTCR value changes from 1 to 0, and transfer ends
• When a repeat area overflow interrupt is requested, and transfer ends
• When an NMI interrupt is generated, and transfer halts
• A reset
• Hardware standby mode
• When 0 is written to the EDA bit, and transfer halts