Datasheet

Section 8 EXDMA Controller (EXDMAC)
Page 410 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
8.3 Register Descriptions
The EXDMAC has the following registers.
• EXDMA source address register_2 (EDSAR_2)
• EXDMA destination address register_2 (EDDAR_2)
• EXDMA transfer count register_2 (EDTCR_2)
• EXDMA mode control register_2 (EDMDR_2)
• EXDMA address control register_2 (EDACR_2)
• EXDMA source address register_3 (EDSAR_3)
• EXDMA destination address register_3 (EDDAR_3)
• EXDMA transfer count register_3 (EDTCR_3)
• EXDMA mode control register_3 (EDMDR_3)
• EXDMA address control register_3 (EDACR_3)
8.3.1 EXDMA Source Address Register (EDSAR)
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address
update function is provided that updates the register contents to the next transfer source address
each time transfer processing is performed. In single address mode, the EDSAR value is ignored
when a device with DACK is specified as the transfer source.
The upper 8 bits of EDSAR are reserved; they are always read as 0 and cannot be modified. Only
0 should be written to these bits.
EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which
EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write
to EDSAR for a channel on which EXDMA transfer is in progress. The initial values of EDSAR
are undefined.