Datasheet

Section 7 DMA Controller (DMAC)
Page 404 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Notes: 1. Not supported in the H8S/2424 Group.
2. Not supported in the 5-V version.
Internal address
φ
Internal read signal
External address
HWR, LWR
Internal write signal
TEND
Not output
DMA
read
External write by CPU, etc.
DMA
write
Figure 7.41 Example in which Low Level Is Not Output at TEND Pin