Datasheet

Section 6 Bus Controller (BSC)
Page 262 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.8.11 Byte Access Control
When synchronous DRAM with a ×16-bit configuration is connected, DQMU and DQML are
used for the control signals needed for byte access.
Figures 6.61 and 6.62 show the control timing for DQM, and figure 6.63 shows an example of
connection of byte control by DQMU and DQML.
T
p
SDRAMφ
φ
RAS
CAS
WE
CKE
PALL ACTV NOP NOPWRIT
DQMU
DQML
Lower data bus
Upper data bus
Address bus
T
r
T
c1
T
cl
T
c2
Row address Column address Column address
Precharge-sel
Row address
High
High
High impedance
Figure 6.61 DQMU and DQML Control Timing
(Upper Byte Write Access: SDWCD = 0, CAS Latency 2)