Datasheet

Section 16 I2C Bus Interface 2 (IIC2)
R01UH0310EJ0500 Rev. 5.00 Page 969 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
1 AAS 0 R/W Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA6
to SVA0 in SAR.
[Setting condition]
• When the slave address is detected in slave
receive mode.
• When the general call address is detected in
slave receive mode.
[Clearing condition]
• When 0 is written in AAS after reading AAS = 1
0 ADZ 0 R/W General Call Address Recognition Flag
This bit is valid in slave receive mode.
[Setting condition]
• When the general call address is detected in
slave receive mode.
[Clearing conditions]
• When 0 is written in ADZ after reading ADZ = 1.
16.3.6 Slave Address Register (SAR)
SAR is an 8-bit readable/writable register that sets slave address. When the chip is in slave mode,
if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device.
Bit Bit Name Initial Value R/W Description
7 to 1 SVA6 to
SVA0
All 0 R/W Slave Address 6 to 0
These bits set a unique address in bits SVA6 to
SVA0, differing from the addresses of other slave
devices connected to the I
2
C bus.
0 ⎯ 0 R/W Reserved
This bit is readable/writable. The write value
should always be 0.