Datasheet

Section 16 I2C Bus Interface 2 (IIC2)
R01UH0310EJ0500 Rev. 5.00 Page 965 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
16.3.4 I
2
C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be
received.
Bit Bit Name Initial Value R/W Description
7 TIE 0 R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit
enables or disables the transmit data empty
interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is
disabled.
1: Transmit data empty interrupt request (TXI) is
enabled.
6 TEIE 0 R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end
interrupt (TEI) at the rising of the ninth clock while
the TDRE bit in ICSR is 1. TEI can be canceled by
clearing the TEND bit or the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
5 RIE 0 R/W Receive Interrupt Enable
This bit enables or disables the receive data full
interrupt request (RXI) when a received data is
transferred from ICDRS to ICDRR and the RDRF
bit in ICSR is set to 1. RXI can be canceled by
clearing the RDRF or RIE bit to 0.
0: Receive data full interrupt request (RXI) is
disabled.
1: Receive data full interrupt request (RXI) is
enabled.