Datasheet

Section 16 I2C Bus Interface 2 (IIC2)
Page 958 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
16.3 Register Descriptions
The I
2
C bus interface has the following registers.
Channel 0
• I
2
C bus control register A_0 (ICCRA_0)
• I
2
C bus control register B_0 (ICCRB_0)
• I
2
C bus mode register_0 (ICMR_0)
• I
2
C bus interrupt enable register_0 (ICIER_0)
• I
2
C bus status register_0 (ICSR_0)
• Slave address register_0 (SAR_0)
• I
2
C bus transmit data register_0 (ICDRT_0)
• I
2
C bus receive data register_0 (ICDRR_0)
• I
2
C bus shift register_0 (ICDRS_0)
Channel 1
• I
2
C bus control register A_1 (ICCRA_1)
• I
2
C bus control register B_1 (ICCRB_1)
• I
2
C bus mode register_1 (ICMR_1)
• I
2
C bus interrupt enable register_1 (ICIER_1)
• I
2
C bus status register_1 (ICSR_1)
• Slave address register_1 (SAR_1)
• I
2
C bus transmit data register_1 (ICDRT_1)
• I
2
C bus receive data register_1 (ICDRR_1)
• I
2
C bus shift register_1 (ICDRS_1)