Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Page 898 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
2 IrRxINV 0 R/W IrRx Data Invert
Specifies the logic level of the IrRxD output to be
inverted. When inversion is performed, the high
pulse width specified by bits 6 to 4 becomes the
low pulse width.
0: Transmit data is used as IrRxD output without
change
1: Transmit data is inverted before used as IrRxD
output
1, 0 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
15.3.11 Serial Extension Mode Register (SEMR)
SEMR selects the clock source in asynchronous mode for the SCI_2. The basic clock can be
automatically set by selecting the average transfer rate.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ Undefined ⎯ Reserved
If these bits are read, an undefined value will be
returned and cannot be modified.
3 ABCS 0 R/W Asynchronous basic clock selection (valid only in
asynchronous mode)
Selects the basic clock for 1-bit period in
asynchronous mode.
0: Operates on a basic clock with a frequency of
16 times the transfer rate.
1: Operates on a basic clock with a frequency of 8
times the transfer rate.