Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
R01UH0310EJ0500 Rev. 5.00 Page 895 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Table 15.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
8 10 16 20 25 30 33
Bit
Rate
(bit/s)
n N n N n N n N n N n N n N
110
250 3 124 ⎯ ⎯ 3 249
500 2 249 ⎯ ⎯ 3 124 ⎯ ⎯ 3 233
1 k 2 124 ⎯ ⎯ 2 249 ⎯ ⎯ 3 97 3 116 3 128
2.5 k 1 199 1 249 2 99 2 124 2 155 2 187 2 205
5 k 1 99 1 124 1 199 1 249 2 77 2 93 2 102
10 k 0 199 0 249 1 99 1 124 1 155 1 187 1 205
25 k 0 79 0 99 0 159 0 199 0 249 1 74 1 82
50 k 0 39 0 49 0 79 0 99 0 124 0 149 0 164
100 k 0 19 0 24 0 39 0 49 0 62 0 74 0 82
250 k 0 7 0 9 0 15 0 19 0 24 0 29 0 32
500 k 0 3 0 4 0 7 0 9 ⎯ ⎯ 0 14 ⎯ ⎯
1 M 0 1 0 3 0 4 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
2.5 M 0 0
*
0 1 ⎯ ⎯ 0 2 ⎯ ⎯
5 M 0 0
*
⎯ ⎯ ⎯ ⎯ ⎯ ⎯
[Legend]
Blank: Cannot be set.
⎯: Can be set, but there will be a degree of error.
*: Continuous transfer is not possible.
Table 15.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s) φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
8 1.3333 1333333.3 18 3.0000 3000000.0
10 1.6667 1666666.7 20 3.3333 3333333.3
12 2.0000 2000000.0 25 4.1667 4166666.7
14 2.3333 2333333.3 30 5.0000 5000000.0
16 2.6667 2666666.7 33 5.5000 5500000.0