Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Page 888 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
15.3.8 Smart Card Mode Register (SCMR)
SCMR selects Smart Card interface mode and its format.
Bit Bit Name Initial Value R/W Description
7 BCP2 1 R/W Basic Clock Pulse 2
Selects, in combination with the BCP1 and BCP0
bits in SMR, the number of basic clock cycles in a
1-bit transfer interval in Smart Card interface
mode.
For the settings, refer to section 15.3.5, Serial
Mode Register (SMR).
6 to 4 ⎯ All 1 ⎯ Reserved
These bits are always read as 1.
3 SDIR 0 R/W Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
2 SINV 0 R/W Smart Card Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the parity
bit. To invert the parity bit, invert the O/E bit in
SMR.
0: TDR contents are transmitted as they are.
Receive data is stored as it is in RDR.
1: TDR contents are inverted before being
transmitted. Receive data is stored in inverted
form in RDR.
1 ⎯ 1 ⎯ Reserved
This bit is always read as 1.
0 SMIF 0 R/W Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
synchronous mode
1: Smart Card interface mode