Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
R01UH0310EJ0500 Rev. 5.00 Page 883 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
2 TEND 1 R Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading
TDRE = 1
• When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
1 MPB 0 R Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
0 MPBT 0 R/W Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
Note: * Only 0 can be written, to clear the flag.