Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
Page 880 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
15.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Bit Bit Name Initial Value R/W Description
7 TDRE 1 R/(W)
*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR,
and data writing to TDR is enabled.
[Clearing conditions]
• When 0 is written to TDRE after reading
TDRE = 1
• When the DMAC or DTC is activated by a TXI
interrupt request and transfers data to TDR
6 RDRF 0 R/(W)
*
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
• When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
• When 0 is written to RDRF after reading
RDRF = 1
• When the DMAC or DTC is activated by an
RXI interrupt and transferred data from RDR
The RDRF flag is not affected and retains its
previous value when the RE bit in SCR is cleared
to 0. Exercise care because if reception of the
next data is completed while the RDRF flag is set
to 1, an overrun error occurs and receive data will
be lost.