Datasheet

Section 15 Serial Communication Interface (SCI, IrDA)
R01UH0310EJ0500 Rev. 5.00 Page 871 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
15.3.3 Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR for only once after confirming that
the TDRE bit in SSR is set to 1.
15.3.4 Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot
be directly accessed by the CPU.
15.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock
source. Some bit functions of SMR differ in normal serial communication interface mode and
Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF bit in SCMR is 0)
Bit Bit Name Initial Value R/W Description
7 C/A 0 R/W Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6 CHR 0 R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is
fixed and the MSB (bit 7) of TDR is not
transmitted in transmission.
In clocked synchronous mode, a fixed data length
of 8 bits is used.