Datasheet

Section 14 Watchdog Timer (WDT)
R01UH0310EJ0500 Rev. 5.00 Page 863 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
14.6.2 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the next cycle after the T
2
state of a TCNT write
cycle, the write takes priority and the timer counter is not incremented. Figure 14.5 shows this
operation.
Address
φ
Internal write signal
TCNT input clock
TCNT
N
M
T
1
T
2
Next cycle
TCNT write cycle
Counter write data
Figure 14.5 Contention between TCNT Write and Increment
14.6.3 Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.