Datasheet

Section 14 Watchdog Timer (WDT)
R01UH0310EJ0500 Rev. 5.00 Page 857 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
14.3.3 Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Bit Bit Name Initial Value R/W Description
7 WOVF 0 R/(W)
*
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
6 RSTE 0 R/W Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR
in WDT are reset)
1: Reset signal is generated if TCNT overflows
5 ⎯ 0 R/W Reserved
Can be read and written, but does not affect
operation.
4 to 0 ⎯ All 1 ⎯ Reserved
These bits are always read as 1 and cannot be
modified.
Note: * Only a write of 0 is permitted, to clear the flag.