Datasheet

Section 14 Watchdog Timer (WDT)
Page 854 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal*
WDTOVF
Reset
control
RSTCSR TCNT TSCR
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR:
TCNT:
RSTCSR:
Note: * An internal reset signal can be generated by the register setting.
Timer control/status register
Timer counter
Reset control/status register
WDT
[Legend]
Internal bus
Figure 14.1 Block Diagram of WDT
14.2 Input/Output Pin
Table 14.1 shows the WDT pin configuration.
Table 14.1 Pin Configuration
Name Symbol I/O Function
Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog
timer mode