Datasheet

Section 13 8-Bit Timers (TMR)
Page 832 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.3.5 Timer Counter Control Register (TCCR)
TCCR selects the TCNT internal clock source and controls the external reset input.
Bit Bit Name Initial Value R/W Description
7 to 4 ⎯ All 0 R Reserved
These bits are always read as 0 and cannot be
modified.
3 TMRIS 0 R/W Timer Reset Input Select
Selects the external reset input, in combination
with the CCLR1 and CCLR0 bits in TCR. See
table 13.2.
2 ⎯ 0 R Reserved
This bit is always read as 0 and cannot be
modified.
1
0
ICKS1
ICKS0
0
0
R/W
R/W
Internal Clock Select 1, 0
These bits select the internal clock source, in
combination with the CKS2 to CKS0 bits in TCR.
See table 13.3.
Table 13.2 Reset Input to TCNT and Clearing Condition
TCR TCCR
Bit 1
CCLR1
Bit 0
CCLR0
Bit 3
TMRIS
Description
0 0 0 Clearing is disabled
0 1 0 Clear by compare match A
1 0 0 Clear by compare match B
1 1 0 Clear by rising edge of external reset input
0 0 1 Clear by both rising and falling edges of external reset input
0 1 1 Clear by falling edge of external reset input
1 0 1 Clear by low level of external reset input
1 1 1 Clear by high level of external reset input