Datasheet

Section 13 8-Bit Timers (TMR)
R01UH0310EJ0500 Rev. 5.00 Page 831 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
13.3.4 Timer Control Register (TCR)
TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts.
Bit Bit Name Initial Value R/W Description
7 CMIEB 0 R/W Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests (CMIB)
are enabled or disabled when the CMFB flag in
TCSR is set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
6 CMIEA 0 R/W Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests (CMIA)
are enabled or disabled when the CMFA flag in
TCSR is set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5 OVIE 0 R/W Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI)
are enabled or disabled when the OVF flag in
TCSR is set to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4
3
CCLR1
CCLR0
0
0
R/W
R/W
Counter Clear 1 and 0
These bits select the method by which TCNT is
cleared, in combination with the TMRIS bit in
TCCR. See table 13.2.
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
These bits select the clock input to TCNT and
the count condition, in combination with the
ICKS1 and ICKS0 bits in TCCR. See table 13.3.