Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0310EJ0500 Rev. 5.00 Page 801 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
11.10.11 Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 11.53 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
Counter
clearing signal
TCNT input
clock
φ
TCNT
TGF
Disabled
TCFV
H'FFFF H'0000
Figure 11.53 Contention between Overflow and Counter Clearing