Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0310EJ0500 Rev. 5.00 Page 797 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
11.10.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T
2
state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 11.49 shows the timing in this case.
Compare
match signal
Write signal
Address
φ
Buffer register
address
Buffer
register
TGR write cycle
T
1
T
2
N
TGR
NM
Buffer register write data
Figure 11.49 Contention between Buffer Register Write and Compare Match