Datasheet
Section 11 16-Bit Timer Pulse Unit (TPU)
R01UH0310EJ0500 Rev. 5.00 Page 781 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Unit Channel Name Interrupt Source
Interrupt
Flag
DTC
Activation
DMAC
Activation
1 6 TGI6A TGRA_6 input capture/compare match TGFA_6 Possible Not possible
TGI6B TGRB_6 input capture/compare match TGFB_6 Possible Not possible
TGI6C TGRC_6 input capture/compare match TGFC_6 Possible Not possible
TGI6D TGRD_6 input capture/compare match TGFD_6 Possible Not possible
TCI6V TCNT_6 overflow TCFV_6 Not possible Not possible
7 TGI7A TGRA_7 input capture/compare match TGFA_7 Possible Not possible
TGI7B TGRB_7 input capture/compare match TGFB_7 Possible Not possible
TCI7V TCNT_7 overflow TCFV_7 Not possible Not possible
TCI7U TCNT_7 underflow TCFU_7 Not possible Not possible
8 TGI8A TGRA_8 input capture/compare match TGFA_8 Possible Not possible
TGI8B TGRB_8 input capture/compare match TGFB_8 Possible Not possible
TCI8V TCNT_8 overflow TCFV_8 Not possible Not possible
TCI8U TCNT_8 underflow TCFU_8 Not possible Not possible
9 TGI9A TGRA_9 input capture/compare match TGFA_9 Possible Not possible
TGI9B TGRB_9 input capture/compare match TGFB_9 Possible Not possible
TGI9C TGRC_9 input capture/compare match TGFC_9 Possible Not possible
TGI9D TGRD_9 input capture/compare match TGFD_9 Possible Not possible
TCI9V TCNT_9 overflow TCFV_9 Not possible Not possible
10 TGI10A TGRA_10 input capture/compare match TGFA_10 Possible Not possible
TGI10B TGRB_10 input capture/compare match TGFB_10 Possible Not possible
TCI10V TCNT_10 overflow TCFV_10 Not possible Not possible
TCI10U TCNT_10 underflow TCFU_10 Not possible Not possible
11 TGI11A TGRA_11 input capture/compare match TGFA_11 Possible Not possible
TGI11B TGRB_11 input capture/compare match TGFB_11 Possible Not possible
TCI11V TCNT_11 overflow TCFV_11 Not possible Not possible
TCI11U TCNT_11 underflow TCFU_11 Not possible Not possible
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.