Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Page 746 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
11.3.9 Timer Synchronous Register (TSYR)
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit Bit Name Initial value R/W Description
7
6
⎯
⎯
0
0
⎯
⎯
Reserved
The write value should always be 0.
5
4
3
2
1
0
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Timer Synchronization 5 to 0
These bits select whether operation is independent
of or synchronized with other channels.
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by
means of bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting/clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)