Datasheet

Section 10 I/O Ports
Page 694 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
10.18.2 Port Function Control Register 1 (PFCR1)
PFCR1 enables or disables address output (A23 to A16).
Bits 7 to 5 are valid in modes 1 and 2 and all the bits are valid in modes 4 and 7.
Bit Bit Name Initial Value R/W Description
7 A23E 1 R/W Address 23 Enable
Enables or disables output for address output 23
(A23).
0: DR output when PA7DDR = 1
1: A23 output when PA7DDR = 1
6 A22E 1 R/W Address 22 Enable
Enables or disables output for address output 22
(A22).
0: DR output when PA6DDR = 1
1: A22 output when PA6DDR = 1
5 A21E 1 R/W Address 21 Enable
Enables or disables output for address output 21
(A21).
0: DR output when PA5DDR = 1
1: A21 output when PA5DDR = 1
4 A20E 1 R/W Address 20 Enable
Enables or disables output for address output 20
(A20).
0: DR output when PA4DDR = 1
1: A20 output when PA4DDR = 1
3 A19E 1 R/W Address 19 Enable
Enables or disables output for address output 19
(A19).
0: DR output when PA3DDR = 1
1: A19 output when PA3DDR = 1
2 A18E 1 R/W Address 18 Enable
Enables or disables output for address output 18
(A18).
0: DR output when PA2DDR = 1
1: A18 output when PA2DDR = 1