Datasheet

Section 10 I/O Ports
Page 690 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
10.17 Port J
Note: Port J is not supported in the H8S/2424 Group and in the 145-pin package.
Port J is a 3-bit I/O port. Port J has the following registers.
• Port J data direction register (PJDDR)
• Port J data register (PJDR)
• Port J register (PORT3)
• Port J open drain control register (PJODR)
10.17.1 Port J Data Direction Register (PJDDR)
The individual bits of PJDDR specify input or output for the pins of port J. PJDDR cannot be read;
if it is, an undefined value will be read.
Bit Bit Name Initial Value R/W Description
7 to 2 ⎯ All 0 ⎯ Reserved
1 PJ1DDR 0 W
0 PJ0DDR 0 W
When a pin function is specified as a general
purpose I/O, setting this bit to 1 makes the
corresponding pin an output port, while clearing this
bit to 0 makes the corresponding pin an input port.
10.17.2 Port J Data Register (PJDR)
PJDR stores output data for the port J pins.
Bit Bit Name Initial Value R/W Description
7 to 2 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
1 PJ1DR 0 R/W
0 PJ0DR 0 R/W
Output data for a pin is stored when the pin function
is specified as a general purpose I/O.