Datasheet

Section 10 I/O Ports
Page 688 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• PH1/CS5/RAS5*
2
/SDRAMφ*
1
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit SDPSTP in
SCKCR of the clock pulse generator, bit CS5E in PFCR0 and bit PH1DDR.
SDPSTP 1 0
Operating
mode
1, 2, 4 3, 7 ⎯
EXPE ⎯ 0 1 ⎯
OEE 0 1 ⎯ 0 1 ⎯
OES ⎯ 0 ⎯ ⎯ 0 ⎯
RMTS2 to
RMTS0
Area 5 is normal space Area 5 is DRAM
space
⎯ Area 5 is normal space Area 5 is DRAM
space
⎯
CS5E 0 1 0 1 ⎯ 0 1 0 1 ⎯
PH1DDR 0 1 0 1 0 1 ⎯ 0 1 0 1 0 1 0 1 ⎯ ⎯
Pin
function
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5*
2
output
PH1
input
PH1
output
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
RAS5*
2
output
SDRAMφ
output*
1
Notes: 1. Not supported in the H8S/2426 Group.
2. Not supported in the 5-V version.