Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 681 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• PG2/CS2/RAS2*
2
/RAS*
1
The pin function is switched as shown below according to the combination of the operating
mode, bits RMTS2 to RMTS0 in DRAMCR of the bus controller, bit CS2E in PFCR0, and bit
PG2DDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CS2E 0 1 ⎯ 0 1
RMTS2 to
RMTS0
⎯ Area 2 is in
normal space
Area 2 is in
DRAM space,
areas 2 to 5
are in
continuous
DRAM space
Areas 2 to
5 are in
synchro-
nous
DRAM
space
⎯ ⎯ Area 2 is in
normal space
Area 2 is in
DRAM space,
areas 2 to 5
are in
continuous
DRAM space
Areas 2 to
5 are in
synchro-
nous
DRAM
space
PG2DDR 0 1 0 1 ⎯ ⎯ 0 1 0 1 0 1 ⎯ ⎯
Pin function PG2
input
PG2
output
PG2
input
CS2
output
RAS2*
2
output
RAS*
1
output
PG2
input
PG2
output
PG2
input
PG2
output
PG2
input
CS2
output
RAS2*
2
output
RAS*
1
output
Notes: 1. Not supported in the H8S/2426 Group and H8S/2424 Group.
2. Not supported in the 5-V version.
• PG1/CS1, PG0/CS0
The pin function is switched as shown below according to the combination of the operating
mode, bit CSnE in PFCR0, and bit PGnDDR.
Operating
mode
1, 2, 4 3, 7
EXPE ⎯ 0 1
CSnE 0 1 ⎯ 0 1
PGnDDR 0 1 0 1 0 1 0 1 0 1
Pin
function
PGn
input
PGn
output
PGn
input
CSn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
[Legend]
n = 1 or 0