Datasheet

Section 10 I/O Ports
Page 672 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• PF0/WAIT-A/ADTRG0-B/SCS0-C/OE-A*
8
(H8S/2424 Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bit WAITE in BCR of the bus controller, bit OEE in DRAMCR*
8
, bits MSS,
CSS1, and CSS0 in SSCRH and bit SSUMS in SSCRL of the SSU, bits TRGS1, TRGS0, and
EXTRGS in ADCR_0 of the ADC, bit OES in PFCR2, bits ADTRG0S and WAITS in PFCR4,
bits SCS0S1 and SCS0S0 in PFCR5, and bit PF0DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
OEE 0
RMTS2 to
RMTS0
⎯
WAITE 0 1
WAITS ⎯ 0 1
SSU settings (1) in table below (2) in
table
below
(4) in
table
below
(3) in
table
below
⎯ (1) in
table
below
⎯ (2) in
table
below
(3) (4) in
table
below
PF0DDR 0 1 0*
8
0*
8
⎯ ⎯ 0 1 0*
8
0
PF0 input PF0
output
SCS0-C
input*
3
*
7
SCS0-C
I/O*
5
*
7
SCS0-C
output*
4
*
7
WAIT-A
input
PF0 input Setting
prohibited
SCS0-C
input*
4
Setting
prohibited
Pin function
ADTRG0-B input*
2
OEE 1
RMTS2 to
RMTS0
Settings other than that for areas 2 to 5 as DRAM Areas 2 to
5 are
DRAM
space
WAITE 0 1 ⎯
WAITS ⎯ 0 1 ⎯
SSU settings (1) in table below (2) in
table
below
(4) in
table
below
(3) in
table
below
⎯ (1) in
table
below
⎯ (2) in
table
below
(3) (4) in
table
below
⎯
PF0DDR 0 1 0*
8
0*
8
⎯ ⎯ 0 1 0*
8
0 ⎯
PF0 input PF0
output
SCS0-C
input*
3
*
7
SCS0-C
I/O*
5
*
7
SCS0-C
output*
4
*
7
WAIT-A
input
PF0 input Setting
prohibited
SCS0-C
input*
3
*
7
Setting
prohibited
OE-A
output*
1
*
8
Pin function
ADTRG0-B input*
2