Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 669 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• Modes 3 and 7 (EXPE = 0)
Areas 2 to 5 ⎯
CS5E ⎯
SSU settings (1) in table below (2) in table below (3) in table below
PF1DDR 0 1 0*
3
⎯
Pin function PF1 input PF1 output SSCK0-C input*
1
*
4
SSCK0-C output*
2
Notes: 1. When using as SSCK0-C input, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before
other register setting.
2. When using as SSCK0-C output, set SSCK0S1 and SSCK0S0 in PFCR5 to B'10 before
other register setting.
3. PF1DDR = 0 when the SSU pin is used as input.
4. Do not set up for SSU unless SSCK0S1 and SSCK0S0 = B'10 in PFCR5.
Use as I/O port.
5. Not supported in the 5-V version.
SSU settings (1) (2) (1) (3) (1) (2) (1) (3)
SSUMS 0 1
MSS 0 1 0 1
SCKS 0 1 0 1 0 1 0 1
Pin state ⎯ SSCK
input
⎯ SSCK
output
⎯ SSCK
input
⎯ SSCK
output
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Note: See tables 19.4 to 19.6.