Datasheet

Section 10 I/O Ports
Page 668 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
SSU settings (1) (2) (1) (3) (1) (2) (1) (3)
SSUMS 0 1
MSS 0 1 0 1
SCKS 0 1 0 1 0 1 0 1
Pin state ⎯ SSCK
input
⎯ SSCK
output
⎯ SSCK
input
⎯ SSCK
output
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Note: See tables 19.4 to 19.6.
• PF1/CS5/UCAS*
5
/SSCK0-C (H8S/2424 Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and SCKS in SSCRH and bit SSUMS in SSCRL of the SSU, bits
RMTS2 to RMTS0 in DRAMCR*
5
of the bus controller, bit CS5E in PFCR0, bits SSCK0S1
and SSCK0S0 in PFCR5, and bit PF1DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
Areas 2 to 5 Any of areas 2 to 5 is
DRAM space
Areas 2 to 5 are all normal space
CS5E ⎯ 0 1
SSU settings ⎯ (1) in table
below
(2) in table
below
(3) in table
below
⎯
PF1DDR ⎯ 0 1 0*
3
⎯ 0 1
Pin function UCAS*
5
output PF1
input
PF1
output
SSCK0-C
input*
1
*
4
SSCK0-C
output*
2
*
4
PF1
input
CS5
output