Datasheet

Section 10 I/O Ports
R01UH0310EJ0500 Rev. 5.00 Page 665 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
SSU
settings
(1) (1) (3) (3) (2) (1) (2) (1) (1) (1) (1) (2) (1) (2) (2) (1) (2)
SSUMS 0 0 1*
1
BIDE 0 1*
2
0
MSS 0 1 0 1 0 1
TE 0 1 0 1 0 1 0 1 0 1 0 1
RE 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1
Pin state ⎯ ⎯ SSI
output
SSI
output
SSI
input
⎯ SSI
input
⎯ ⎯ ⎯ ⎯ SSI
input
⎯ SSI
input
SSI
input
⎯ SSI
input
[Legend]
⎯: Not used as the SSU pin (can be used as an I/O port).
Notes: See tables 19.4 to 19.6.
1. Do not set BIDE to 1 when SSUMS = 1 in SSU.
2. Do not specify that TE = RE = 1 when operating with BIDE = 1 (bidirectional mode).
• PF2/CS6/LCAS*
5
/SSI0-C (H8S/2424 Group)
The pin function is switched as shown below according to the combination of the operating
mode, bit EXPE, bits MSS and BIDE in SSCRH, bit SSUMS in SSCRL, and bits TE and RE
in SSER of the SSU, bits RMTS2 to RMTS0 in DRAMCR*
5
of the bus controller, bit CS6E in
PFCR0, bits SSI0S1 and SSI0S0 in PFCR5, bits ABW5 to ABW2 in ABWCR, and bit
PF2DDR.
• Modes 1, 2, and 4 Modes 3 and 7 (EXPE = 1)
Areas 2 to 5 Any DRAM/
synchronous DRAM
space area is 16-bit
bus space
All DRAM/synchronous DRAM space areas are
8-bit bus space, or areas 2 to 5 are all normal space
CS6E ⎯ 0 1
SSU settings ⎯ (1) in table below (2) in
table
below
(3) in
table
below
⎯
PF2DDR ⎯ 0 1 0*
3
⎯ 0 1
Pin function LCAS*
5
output PF2
input
PF2
output
SSI0-C
input*
1
*
4
SSI0-C
output*
2
*
4
PF2
input
CS6
output